JTAG Port

BYPASS— (IR = $4, $5,

$7, $8, $9, $B, $C, $D, $E,

0

$F) JTAG Bypass

Register

Reset = $0 * Indicates reserved bits, written as 0 for future compatibility Read/Write

AA1394

Figure 13-2. JTAG Port Programming Model

13.2.1 JTAG Instruction Register (IR) and Decoder

The TAP controller contains a 4-bit instruction register (IR). The instruction is presented to an instruction decoder during the Update-IR state. See Section 13.3, “TAP Controller,” for a description of the TAP controller operating states. The instruction decoder interprets and executes the instructions according to the conditions defined by the TAP controller state machine. The DSP56824 includes the three mandatory public instructions (BYPASS, SAMPLE/PRELOAD, and EXTEST) and six public instructions (CLAMP, HIGHZ, EXTEST_PULLUP, IDCODE, ENABLE_ONCE, and DEBUG_REQUEST).

The 4 bits B[3:0] of the IR decode the nine instructions, as shown in Table 13-2. All other encodings are reserved.

JTAG Port Architecture

WARNING:

Reserved JTAG instruction encodings should not be used. Hazardous operation of the chip could occur if these instructions are used.

The JTAG IR is reset to 0010 in the test-logic-reset controller state. Therefore, the IDCODE instruction is selected on JTAG reset. In the Capture-IR state, the two least significant bits (LSBs) of the instruction shift register are preset to 01, where the 1 is in the LSB location as required by the standard. The two most significant bits (MSBs) may either capture status or be set to 0. New instructions are shifted into the instruction shift register stage on Shift-IR state.

13.2.1.1 EXTEST (B[3:0] = 0000)

The external test (EXTEST) instruction enables the BSR between TDI and TDO, including cells for all digital device signals and associated control signals. The EXTAL pin and any codec pins associated with analog signals are not included in the BSR path.

In EXTEST, the BSR is capable of scanning user-defined values onto output pins, capturing values presented to input signals, and controlling the direction and value of bidirectional pins. The EXTEST instruction asserts internal system reset for the DSP system logic for the duration of EXTEST in order to force a predictable internal state while performing external boundary-scan operations.

13.2.1.2 SAMPLE/PRELOAD (B[3:0] = 0001)

The SAMPLE/PRELOAD instruction enables the BSR between TDI and TDO. When this instruction is selected, the operation of the test logic has no effect on the operation of the on-chip system logic or on the flow of a signal between the system pin and the on-chip system logic, as specified by IEEE 1149.1a-1993. This instruction provides two separate functions. First, it provides a means to obtain a snapshot of system data and control signals (SAMPLE). The snapshot occurs on the rising edge of TCK in the Capture-DR controller state. The data can be observed by shifting it transparently through the BSR. In a normal system configuration, many signals require external pull ups to ensure proper system operation. Consequently, the same is true for the SAMPLE/PRELOAD functionality. The data latched into the BSR during the Capture-DR controller state may not match the drive state of the package signal if the system-required pull ups are not present within the test environment.

JTAG Port

The second function of the SAMPLE/PRELOAD instruction is to initialize the BSR output cells (PRELOAD) prior to the selection of the CLAMP, EXTEST, or EXTEST_PULLUP instruction. This initialization ensures that known data appears on the outputs when executing EXTEST. The data held in the shift register stage is transferred to the output latch on the falling edge of TCK in the Update-DR controller state. Data is not presented to the pins until the CLAMP, EXTEST, or EXTEST_PULLUP instruction is executed.

NOTE:

Since there is no internal synchronization between the JTAG clock (TCK) and the system clock (CLK), the user must provide some form of external synchronization to achieve meaningful results when sampling system values using the SAMPLE/PRELOAD instruction.

13.2.1.3 IDCODE (B[3:0] = 0010)

The IDCODE instruction enables the IDREGISTER between TDI and TDO. It is provided as a public instruction to allow the manufacturer, part number, and version of a component to be determined through the TAP.

When the IDCODE instruction is decoded, it selects the IDREGISTER, a 32-bit test data register. IDREGISTER loads a constant logic one into its LSB. Since the bypass register loads a logic zero at the start of a scan cycle, examination of the first bit of data shifted out of a component during a test data scan sequence immediately following exit from the test-logic-reset controller state shows whether an IDREGISTER is included in the design.

When the IDCODE instruction is selected, the operation of the test logic has no effect on the operation of the on-chip system logic, as required in IEEE 1149.1a-1993.

13.2.1.4 EXTEST_PULLUP (B[3:0] = 0011)

The EXTEST_PULLUP instruction is provided as a public instruction to aid in fault diagnoses during boundary-scan testing of a circuit board. This instruction functions similarly to EXTEST, with the only difference being the presence of a weak pull-up device on all input signals. Given an appropriate charging delay, the pull-up current supplies a deterministic logic one result on an open input. When this instruction is used in board-level testing with heavily loaded nodes, it may require a charging delay greater than the two TCK periods needed to transition from the Update-DR state to the Capture-DR state. Two methods of providing an increase delay are available: traversing into the run-test/idle state for extra TCK periods of charging delay, or limiting the maximum TCK frequency (slow down the TCK) so that two TCK periods are adequate. The EXTEST_PULLUP instruction asserts internal system reset for the DSP system logic for the duration of EXTEST_PULLUP in order to force a predictable internal state while performing external boundary-scan operations.

13.2.1.5 HIGHZ (B[3:0] = 0100)

The HIGHZ instruction enables the single-bit bypass register between TDI and TDO. It is provided as a public instruction in order to prevent having to drive the output signals back during circuit board testing. When the HIGHZ instruction is invoked, all output drivers are placed in an inactive-drive state. HIGHZ asserts internal system reset for the DSP system logic for the duration of HIGHZ in order to force a predictable internal state while performing external boundary-scan operations.

JTAG Port Architecture

13.2.1.6 CLAMP (B[3:0] = 0101)

The CLAMP instruction enables the single-bit bypass register between TDI and TDO. It is provided as a public instruction. When the CLAMP instruction is invoked, the package output signals respond to the preconditioned values within the update latches of the BSR, even though the bypass register is enabled as the test data register. In-circuit testing can be facilitated by setting up guarding signal conditions that control the operation of logic not involved in the test with use of the SAMPLE/PRELOAD or EXTEST instructions. When the CLAMP instruction is executed, the state and drive of all signals remain static until a new instruction is invoked. A feature of the CLAMP instruction is that while the signals continue to supply the guarding inputs to the in-circuit test site, the bypass mode is enabled, thus minimizing overall test time. Data in the boundary-scan cell remains unchanged until a new instruction is shifted in or the JTAG state machine is set to its reset state. CLAMP asserts internal system reset for the DSP system logic for the duration of CLAMP in order to force a predictable internal state while performing external boundary-scan operations.

13.2.1.7 ENABLE_ONCE (B[3:0] = 0110)

The ENABLE_ONCE instruction enables the JTAG port to communicate with the OnCE state machine and registers. It is provided as a Motorola public instruction to allow the user to perform system debug functions. When the ENABLE_ONCE instruction is invoked, the TDI and TDO pins are connected directly to the OnCE registers. The particular OnCE register connected between TDI and TDO is selected by the OnCE state machine and the OnCE instruction being executed. All communication with the OnCE instruction controller is done through the Select-DR-Scan path of the JTAG state machine. Refer to the

DSP56800 Family Manual for more information.

13.2.1.8 DEBUG_REQUEST (B[3:0] = 0111)

The DEBUG_REQUEST instruction asserts a request to halt the core for entry to debug mode. It is typically used in conjunction with ENABLE_ONCE to perform system debug functions. It is provided as a Motorola public instruction. When the DEBUG_REQUEST instruction is invoked, the TDI and TDO pins are connected to the bypass register. Refer to the DSP56800 Family Manual for more information.

13.2.1.9 BYPASS (B[3:0] = 1111)

The BYPASS instruction enables the single-bit bypass register between TDI and TDO, as shown in Figure 13-3. This creates a shift register path from TDI to the bypass register and finally to TDO, circumventing the BSR. This instruction is used to enhance test efficiency by shortening the overall path between TDI and TDO when no test operation of a component is required. In this instruction, the DSP system logic is independent of the TAP. When this instruction is selected, the test logic has no effect on the operation of the on-chip system logic, as required in IEEE 1149.1a-1993.

TDI

D Q To TDO MUX

SHIFT_DR

CLOCK_DR CK

AA0122

Figure 13-3. Bypass Register