OnCE Unit Low-Power Operation

Example 12-8. Jump to a New Program—Go from Address $xxxx (Continued)

7.Send 16 bits of the target absolute address ($xxxx). The chip will resume fetching from the target address (with no pipeline problems). The trace counter will count this instruction, so the current trace counter may need to be corrected if the trace mode enable bit in the OSCR has been set.

In other words, after 16 bits have been received, the PDB drives the OPDBR. ODEC releases the chip from the halt state, and the debug mode bit in OSCR is cleared. The chip executes first the jump instruction and then fetches the instruction from the target address. The chip continues to execute instructions from that address until a debug mode condition occurs.

12.12 OnCE Unit Low-Power Operation

If the OnCE module’s debug capability is not required by an application, it is possible to shut off the breakpoint units and the OnCE module for low power consumption. This is done by setting the PWD bit in the OCR register. This prevents the breakpoint units from latching any values for comparison.

12.13 Resetting the Chip Without Resetting the

OnCE Unit

The DSP can be reset without resetting the OnCE module. This allows setting breakpoints on an application’s final target hardware, which may have a power-on reset circuit.

The OnCE module reset is disabled using the following technique. If an ENABLE_ONCE instruction is in the JTAG IR when a hardware or COP timer reset occurs, then the OnCE module unit is not reset. All OnCE module registers retain their current values, and all valid breakpoints remain enabled. If any other instruction is in the JTAG IR when a chip reset occurs, the OnCE module is reset. This capability allows for the following sequence, which is useful for setting breakpoints on final target hardware:

1.Reset the DSP chip using the RESET pin.

2.Come out of reset and begin to execute the application code, perhaps out of program ROM if this is where the user’s application code is located.

3.Halt the DSP chip and enter the debug mode.

4.Program the desired breakpoint(s) and leave the ENABLE_ONCE instruction in the JTAG IR.

5.Reset the DSP chip using the RESET pin again, but this time the OnCE module is not reset and the breakpoints remain valid and enabled.

6.Come out of reset and begin to execute the application code, perhaps out of program ROM if this is where the user’s application code is located. The DSP chip then correctly triggers in the application code when the desired breakpoint condition is detected.

7.Poll the JTAG port to detect the occurrence of this breakpoint.

OnCE™ Module

Another technique for loading breakpoints is accomplished as follows:

1.Reset the DSP chip by asserting both the RESET pin and the TRST pin.

2.Release the TRST pin.

3.Shift an ENABLE_ONCE instruction into the JTAG IR.

4.Set up the desired breakpoints.

5.Release the RESET pin.

6.Come out of reset and begin to execute the application code. The DSP chip then correctly triggers in the application code when the desired breakpoint condition is detected.

7.Poll the JTAG port to detect the occurrence of this breakpoint.

Another useful sequence is to enter the debug mode directly from reset. This is accomplished as follows:

1.Reset the DSP chip by asserting both the RESET pin and the TRST pin.

2.Release the TRST pin.

3.Shift a DEBUG_REQUEST instruction into the JTAG IR.

4.Release the RESET pin.

5.Come out of reset and directly enter the debug mode.

The OnCE module reset can still be forced on DSP chip reset even if there is an ENABLE_ONCE instruction in the JTAG IR. This is accomplished by asserting the TRST pin in addition to the RESET pin, which guarantees reset of the OnCE module.

Chapter 13

JTAG Port

The JTAG port is a dedicated, user-accessible test access port (TAP) that is compatible with the IEEE Standard Test Access Port and Boundary-Scan Architecture (1149.1a-1993). Problems associated with testing high-density circuit boards have led to the development of this proposed standard under the sponsorship of the Test Technology Committee of IEEE and the JTAG. The DSP56824 supports circuit-board test strategies based on this standard.

Five dedicated pins interface to the TAP, which contains a 16-state controller. The TAP uses a boundary-scan technique to test the interconnections between integrated circuits after they are assembled onto a printed circuit board (PCB). Boundary scanning allows a tester to observe and control signal levels at each component pin through a shift register placed next to each pin. This is important for testing continuity and determining if pins are stuck at a one or zero level.

The TAP port has the following capabilities:

•Performing boundary-scan operations to test circuit-board electrical continuity

•Bypassing the DSP for a given circuit-board test by replacing the boundary scan register (BSR) with a single bit register

•Sampling the DSP system pins during operation and transparently shift out the result in the BSR; pre-loading values to output pins prior to invoking the EXTEST instruction

•Disabling the output drive to pins during circuit-board testing

•Providing a means of accessing the OnCE module controller and circuits to control a target system

•Querying identification information (manufacturer, part number, and version) from a DSP chip

•Forcing test data onto the outputs of a DSP IC while replacing its BSR in the serial data path with a single bit register

•Enabling a weak pull-up current device on all input signals of a DSP IC (helping to ensure deterministic test results in the presence of a continuity fault during interconnect testing)

This section includes aspects of the JTAG implementation that are specific to the DSP56824. It is intended to be used with IEEE 1149.1a-1993. The discussion includes those items required by the standard to be defined and, in certain cases, provides additional information specific to the DSP56824. For internal details and applications of the standard, refer to IEEE 1149.1a-1993.