Signal

State

Signal Name

During

Signal Description

Type

Reset

MODB

Input

Input

Mode Select B— During hardware reset, MODA and MODB select

one of the four initial chip operating modes latched into the OMR. Sev-

eral clock cycles (depending on PLL setup time) after leaving the

Reset state, the MODB pin changes to external interrupt request

IRQB.

After reset, the chip operating mode can be changed by soft-

ware.

Input

External Interrupt Request B— The

input is an asynchro-

IRQB

IRQB

nous external interrupt request that indicates that an external

device is requesting service. It can be programmed to be level-sen-

sitive or negative-edge triggered. If level-sensitive triggering is

selected, an external pull-up resistor is required for Wired-OR

operation.

Input

Input

Reset— This input is a direct hardware reset on the processor.

RESET

When

RESET

is asserted low, the DSP is initialized and placed in

the Reset state. A Schmitt trigger input is used for noise immunity.

When the

RESET

pin is deasserted, the initial chip operating mode

is latched from the MODA and MODB pins. The internal reset sig-

nal should be deasserted synchronously with the internal clocks.

To ensure complete hardware reset,

and

RESET

TRST/DE should

be asserted together. The only exception occurs in a debugging

environment when a hardware DSP reset is required and it is nec-

essary not to reset the JTAG/OnCE port. In this case, assert

but do not assert

RESET,

TRST/DE.

Signal

State

Signal Name

During

Signal Description

Type

Reset

PB0–PB7

Input or

Input

Port B GPIO— These eight pins can be programmed to generate

output

an interrupt for any pin programmed as an input when there is a

transition on that pin. Each pin can be configured individually to

recognize a low-to-high or a high-to-low transition. In addition,

these pins are dedicated GPIO pins that can individually be pro-

grammed as input or output pins.

After reset, the default state is GPIO input.

2-6

DSP56824 User’s Manual