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Accessing the OnCE Module

Register

16-bit read/write?

 

no

 

 

 

 

 

Select

8-bit shifter selected

 

 

 

 

 

 

 

 

 

 

 

 

JTAG

Test/Idle-Run

DR-Select-Scan

-CaptureDR

 

 

Shift-DR

 

 

 

 

DR-Exit1

DR-Update

DR-Select-Scan

-CaptureDR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TCK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TMS

TDI

TDO

 

= Don’t Care

 

 

 

 

 

= Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

8-bit shifter selected

Shift-DR

UpdateDR-

Exit1DR-

AA0847

Figure 12-23. OSR Status Polling

On the first 8-bit sequence, $00 is shifted into the OCMDR, which corresponds to no register selected. Next, $00 is read out from the OSR, indicating the DSP core is still in normal mode. The OnCE module decodes the $00 opcode and again selects the 8-bit shifter, since no 16-bit access is associated with this opcode. On the second 8-bit sequence, $1A is read from the OSR, indicating that the chip is in debug mode and a hardware breakpoint has occurred.

12.10.4.5 JTAG IR Status Polling

OSR status polling has some disadvantages. First, the OSR is not accessible when the DSP is executing a STOP instruction. OSR access (and all other OnCE register accesses) can continue only after the stop state has been exited, either by an interrupt or a by DEBUG_REQUEST. Second, 8-bit shifts are required.

Polling the JTAG IR provides a more efficient and more reliable means of gathering status information. The following sequence shows how the JTAG IR can be polled. Again, assume a breakpoint has been set up to halt the core. See Figure 12-24.

 

OnCE™ Module

12-47

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