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OnCE™ Module

Register

16-bit read/write?

 

 

yes, 16-bit write

8-bit shifter selected

 

 

 

 

 

 

 

 

Select

8-bit shifter selected

 

 

 

16-bit shifter selected

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

JTAG

State

TCK

TMS

TDI

TDO

Test/Idle-Run

DR-Select-Scan

Capture-DR

 

 

 

Shift-DR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

= Don’t Care or Unspecified

Exit1-DR

Update-DR

Select-DR-Scan

Capture-DR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

= Tri-State

Shift-DR

Update-DR

Exit1-DR

AA0846

Figure 12-22. Executing a OnCE Command by Writing the OCNTR

In this sequence, $00 was read out from the OSR, indicating that the chip is in normal mode (the DSP core is running). The OnCE opcode shifted in is $01, which corresponds to Write OCNTR. In the ensuing 16-bit shift, $0003 is shifted in. Since the OCNTR is only 8 bits wide, it loads the 8 least significant bits, or $03. The bits coming out of TDO are unspecified during 16-bit writes.

12.10.4.4 OSR Status Polling

As described in the previous examples, status information from the OSR is made available each time a new OnCE command is shifted in. This provides a convenient means for status polling. The following sequence shows the OSR status polling. Assume that a breakpoint has been set up to halt the core. See Figure 12-23.

12-46

DSP56824 User’s Manual

 

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