OnCE™ Module

12.10.4.1 JTAG/OnCE Interaction: Basic Sequences

JTAG controls the OnCE module via two basic JTAG instructions: DEBUG_REQUEST and ENABLE_ONCE. DEBUG_REQUEST provides a simple way to halt the DSP core. The halt request is latched in the OnCE module so that a new JTAG instruction can be shifted in without waiting for the request to be granted. After DEBUG_REQUEST has been shifted in, JTAG IR status polling takes place to see if the request has been granted. This polling sequence is described in Section 12.10.4.5, “JTAG IR Status Polling.” Like any other JTAG instruction, DEBUG_REQUEST selects a data register to be connected between TDI and TDO in the DR path. The 1-bit BYPASS register is selected. Values shifted into the BYPASS register have no effect on the OnCE logic.

ENABLE_ONCE is decoded in the JTAG IR for most of the time during a OnCE sequence. When ENABLE_ONCE is decoded, access to the OnCE registers is available through the DR path. Depending on which register is being accessed, the shifter connected between TDI and TDO during Shift-DR can be either 8 or 16 bits long. The shifter is 8 bits long for OCMDR and OSR accesses and 16 bits long for all other register accesses. This means that if the OnCE module is expecting a command to be entered (to be loaded into the OCMDR), an 8-bit shifter is selected. If the OnCE command then loaded into the OCMDR has a 16-bit read or write associated with it, a 16-bit shifter is connected between TDI and TDO during Shift-DR. The OnCE shifter selection can be understood in terms of the state diagram in Figure 12-20.

Idle

UPDATE-IR:ENABLE_ONCE

8-Bit Shifter Selected

(OCMDR/OSR)

16-Bit Read/Write?

Yes

UPDATE_DR

16-Bit Shifter Selected

AA0844

Figure 12-20. OnCE Shifter Selection State Diagram

As long as ENABLE_ONCE is decoded in JTAG IR, one of the two shifters is available for shifting. If a different JTAG instruction is shifted in, the BYPASS register is selected.

12.10.4.2 Executing a OnCE Command by Reading the OCR

The following sequence shows how to read the OCR, assuming that ENABLE_ONCE is being decoded in JTAG IR, the JTAG state machine is at run-test/idle, and the DR path has not yet been entered, meaning that the OnCE module has selected the 8-bit shifter. See Figure 12-21.