Accessing the OnCE Module

Exit1-IR. TDO changes on the falling edges of TCK in Shift-IR. It switches back to tri-state on the falling edge of TCK in Exit1-IR. The first 2 bits shifted out of TDO are constant: first 1, then 0. The following 2 bits are the OnCE status bits, OS[1:0].

NOTE:

The value in OS[1:0] is shifted out whenever a new JTAG instruction is shifted in. This provides a convenient means to obtain status information.

12.10.4 Accessing a JTAG Data Register

JTAG data registers are loaded via the DR path in the state machine. Shifting takes place in the Shift-DR state, and the shifter connected between TDI and TDO is selected by the instruction decoded in the JTAG IR. Data is captured (if applicable) in the selected register on Capture-DR and shifted out on Shift-DR while new data is shifted in, and finally the new data is loaded into the selected register on Update-DR.

Assume that BYPASS has been loaded into the JTAG IR and that the state machine is in the run-test/idle state. In BYPASS, a 1-bit register is selected as the data register. The following sequence shows how data can be shifted through the BYPASS register, as shown in Figure 12-19.

Figure 12-19. Shifting Data through the BYPASS Register

The first bit shifted out of TDO is a constant zero because the BYPASS register captures zero on Capture-DR per the IEEE standard. The ensuing bits are just the bits shifted into TDI, delayed by one period.