OnCE™ Module

12.9.2.5 Exiting Debug Mode

There are three ways to exit debug mode:

•Restore the pipeline by writing the original OPDBR value back to OPDBR twice, first with

GO = EX = 0 and last with GO = EX = 1. PAB is restored from OPABFR so that fetching continues from the correct address.

•Change program flow by writing a jmp opcode to OPDBR with GO = EX = 0 and then writing the target address to OPDBR with GO = 1 and EX = 0. Next, write a NOP to OPDBR with

GO = EX = 1.

•Apply a hardware reset (assert RESET), which brings the chip out of debug mode provided DEBUG_REQUEST is not decoded in the JTAG IR.

12.10 Accessing the OnCE Module

This section describes useful example sequences involving the JTAG/OnCE interface. The sequences are described in a hierarchical manner. Low-level sequences describe basic operations (for example, JTAG instruction and data register accesses). Building on this, the second group of sequences describe more complicated sequences (for example, OnCE command entry and status polling). The final set builds further on the lower-level sequences to describe how to display core registers, set breakpoints, and change memory.

12.10.1 Primitive JTAG Sequences

The JTAG/OnCE serial protocol is identical to the protocol described in the IEEE Standard Test Access Port and Boundary-Scan Architecture (1149.1a-1993). It involves the control of four input pins—TRST (actually bidirectional), TDI, TMS, and TCK—and the observance of one output pin, TDO. TDI and TDO are the serial input and output, respectively. TCK is the serial clock and TMS is an input used to selectively step through the JTAG state machine. TRST is an asynchronous reset of the JTAG port. It is multiplexed with the DE output function.

The following descriptions refer to states in the JTAG state machine diagram in Figure 13-5 on page 13-13. Please refer to this diagram or to the IEEE 1149.1a-1993 document.

12.10.2 Entering the JTAG Test-Logic-Reset State

The test-logic-reset state is the convenient starting point for primitive JTAG/OnCE module sequences. While in this state, JTAG is reset. This means that TDO is disabled, no shifting is taking place, and the JTAG IR is decoding the IDCODE instruction. This state is entered only on power up or during the initial phase of a series of OnCE module sequences. In addition, this state can be entered to get JTAG into a known state. To enter the test-logic-reset state on power up, both TRST and RESET should be asserted, as shown in Figure 12-15. See the DSP56824 Technical Data Sheet for minimum assertion pulse widths. TRST can change at any time with respect to TCK.

Accessing the OnCE Module

JTAG

Test-Logic-Reset

State

TCK

TRST

RESET

TMS

Figure 12-15. Entering the JTAG Test-Logic-Reset State

At any other time, the test-logic-reset state can be entered by holding TMS high for five or more TCK pulses, as shown in Figure 12-16. TMS is sampled by the chip on the rising edge of TCK. To explicitly show this timing, TMS is shown to change on the falling edge of TCK. The JTAG state machine changes state on the rising edges of TCK (or on TRST assertion and power up). This sequence provides a simple way of resetting JTAG into a known state.

Figure 12-16. Holding TMS High to Enter Test-Logic-Reset State