OnCE™ Module

12.8.2 OnCE Trace Logic Operation

The trace logic is tightly coupled with the breakpoint logic, sharing resources where necessary. When BK[4:0] = 10111, OCNTR is decremented each time an instruction is executed from normal mode. Instructions executed from debug mode do not decrement the OCNTR. The event occurrence mechanism is slightly different for trace than for breakpoints. For breakpoints, the event occurs when OCNTR = 0, and another valid address compare happens. For trace, the event occurs (TO is set) when OCNTR first reaches zero. If the EM bits are set for entry to debug mode, one more instruction is executed after TO is set. Therefore, if the user wants to halt the DSP after executing n instructions, n – 1 should be placed in OCNTR (much like the breakpoint case). But if the user would like to halt only the FIFO after n instructions, n should be placed in OCNTR. This is different from the breakpoint case and occurs because the TO flag is set when OCNTR first reaches zero. Trace events cannot cause OnCE interrupts, although TO is set and DE is asserted (pulled low) for this EM (that is, EM = 10 acts just like EM = 11 for trace).

Since trace events occur when OCNTR reaches zero and trace mode is enabled by one of the BK settings, rearming trace events acts differently than rearming breakpoint events. For example, EM = 10 and

EM = 11 encodings attempt to rearm the trace event, but since the conditions are still valid for trace, TO remains set and DE remains low. Similarly, for EM = 01 (FIFO halt), an OCR write attempts to clear the TO, but again the flag remains set since conditions are still valid for trace. To clear TO and capture additional FIFO values, do the following:

1.Write OCR to disable trace (FIFO begins capturing).

2.Write OCNTR with the desired value.

3.Write OCR to enable trace.

4.Poll for TO = 1.

If the first step is omitted, TO is never reset and the FIFO does not begin capturing because the conditions for valid trace are still present.

Note that there are sequential breakpoints that enable trace mode. Their trace mode operation is identical to the BK[4:0] = 10111 operation, except that the HBO bit is set.

A common use of the trace logic is to execute a single instruction (OCNTR = 0) and then immediately return to debug mode. Upon returning to debug mode, the user can display registers or memory locations. When this process is repeated, the user can step through individual instructions and see their effect on the state of the processor.

12.9 The Debug Processing State

A DSP56800 chip in a user application can enter any of six different processing modes:

•Reset mode

•Normal mode

•Exception mode

•Wait mode

•Stop mode

•Debug mode

The first five of these are referenced in Chapter 7, “Interrupts and the Processing States,” in the DSP56800 Family Manual. The last processing mode, the debug mode, is described in this subsection.

The Debug Processing State

The debug mode supports the on-chip emulation features of the chip. In this mode, the DSP core is halted and is set to accept OnCE commands through the JTAG port. Once the OnCE module is set up correctly, the DSP leaves the debug mode and returns control to the user program. The DSP reenters the debug mode when the previously set trigger condition occurs, provided that EM = 00 (OnCE events cause entry to debug mode).

Capabilities available in the debug mode include the following:

•Reading and writing the OnCE registers

•Reading the instruction FIFO

•Resetting the OnCE event counter

•Executing a single DSP instruction and returning to this mode

•Executing a single DSP instruction and exiting this mode

12.9.1 OnCE Normal, Debug, and Stop Modes

The OnCE module has three operational modes: normal, debug, and stop. Whenever a STOP instruction is executed by the DSP, the OnCE module is no longer accessible. The OnCE module is in the normal mode except when the DSP enters the debug mode or is in stop mode. The OnCE module is in debug mode whenever the DSP enters the debug mode. The major difference between the states is register access. The following OnCE module registers can be accessed in normal or debug mode:

•OnCE control register (OCR)

•OnCE status register (OSR)

•OnCE breakpoint and trace counter (OCNTR)

•OnCE breakpoint address register (OBAR)

•OnCE program address bus fetch register (OPABFR) (if FIFO halted)

•OnCE PAB decode register (OPABDR) (if FIFO halted)

•OnCE PAB execute register (OPABER) (if FIFO halted)

•OnCE PAB change-of-flow FIFO (OPFIFO) (if FIFO halted)

The following OnCE registers can only be accessed when the module is in debug mode:

•OnCE peripheral global data bus register (OPGDBR)

•OnCE program data bus register (OPDBR)

If a STOP is executed while the user is accessing OnCE in user mode, problems may occur since few or no internal clocks are running anymore. This should be avoided. The user can recognize the occurrence by capturing the OS bits in the JTAG IR in Capture-IR. The user can then choose to send a DEBUG_REQUEST to bring the core out of STOP.