Interrupt and Mode Control Signals

Table 2-7. Bus Control Signals (Continued)

Signal

State

Signal Name

During

Signal Description

Type

Reset

Output

Pulled

Write Enable—

is asserted low during external memory write

WR

WR

high

cycles. When

WR

is asserted low in T1, the data bus pins D0–D15

internally

become outputs and the DSP puts data on the bus during the lead-

ing edge of T2. When

WR

is deasserted high in T3, the external

data is latched inside the external device. When

WR

is asserted, it

qualifies the A0–A15,

PS,

and

DS

pins.

WR

can be connected

directly to the

WE

pin of a Static RAM. During an internal access in

stop or wait mode, the value of the DRV bit in the BCR determines

whether the chip continues to drive

WR

(DRV = 1) or tri-states

WR

(DRV = 0).

Output

Pulled

Read Enable—

is asserted low during external memory read

RD

RD

high

cycles. When

RD

is asserted low during late T0 or early T1, the

internally

data bus pins D0–D15 become inputs and an external device is

enabled onto the DSP data bus. When

RD

is deasserted high in

T3, the external data is latched in the DSP. When

RD

is asserted, it

qualifies the A0–A15,

PS,

and

DS

pins.

RD

can be connected

directly to the

OE

pin of a Static RAM or ROM. During an internal

access in stop or wait mode, the value of the DRV bit in the BCR

determines whether the chip continues to drive

RD

(DRV = 1) or

tri-states

RD

(DRV = 0).

Signal

State

Signal Name

During

Signal Description

Type

Reset

MODA

Input

Input

Mode Select A— During hardware reset, MODA and MODB select

one of the four initial chip operating modes latched into the operating

mode register (OMR). Several clock cycles (depending on PLL setup

time) after leaving the Reset state, the MODA pin changes to external

interrupt request

IRQA.

The chip operating mode can be changed by

software after reset.

Input

External Interrupt Request A— The

input is an asynchro-

IRQA

IRQA

nous external interrupt request that indicates that an external

device is requesting service. It can be programmed to be level-sen-

sitive or negative-edge triggered. If level-sensitive triggering is

selected, an external pull-up resistor is required for Wired-OR

operation.

If the processor is in the stop state and

is asserted, the pro-

IRQA

cessor will exit the stop state.

Signal Descriptions

2-5