Breakpoint Configuration

Perhaps the most important breakpoint capability is the ability to break on up to two program memory locations, on a sequence where a first found breakpoint is followed sequentially by a second breakpoint, on a specified data memory location when a programmed value is read or written as data to that location, and on a specified data memory location where a programmed value is detected only at masked bits in a data value. Upon detecting a valid event, the OnCE module then performs one of four actions currently available in the OnCE module:

•Halt the DSP core and enter the debug processing state.

•Interrupt the DSP core.

•Halt the OnCE FIFO, but let the DSP core continue operation.

•Rearm the trigger mechanism (and toggle the DE pin).

If a breakpoint is set on the last instruction in a DO loop (even if BS = 00 and BE = 10), a breakpoint match occurs during the execution of the DO instruction as well as during the execution of the instruction at the end of the DO loop.

12.8.1 Programming the Breakpoints

Breakpoints and trace can be configured while the core is executing DSP instructions or while the core is in reset. Complete access to the breakpoint logic (OCNTR, OBAR, and OCR) is provided during these operating conditions. The user could hold the chip in reset; set OCNTR, OBAR, and OCR such that debug mode is entered on a specific condition; release reset; and debug the application. Similarly, the application can be running while the user configures breakpoints to toggle DE on each data memory access to a certain location, allowing the user to gather statistical information.

In general, to set up a breakpoint, the following sequence must be performed:

1.JTAG must be decoding ENABLE_ONCE to allow OnCE module register reads and writes.

2.The PWD bit in the OCR must be cleared to power up the OnCE module, and the BE[1:0] bits in the OCR should be set to 00.

3.The breakpoint address must be written into the OBAR.

4.The value n – 1 must be written into the OCNTR, where n is the number of valid address compares that must take place before generating a OnCE event.

5.The OCR must be written to set the BE, BS, and BK bits for the desired breakpoint conditions, EM to choose what happens when an event occurs, and DE to enable or disable the DE pin.

If these steps are completed while in debug mode, debug mode must be exited to restart the core. If these steps are done in user mode, the breakpoint is set immediately. Note that OnCE events can occur even if ENABLE_ONCE is not latched in the JTAG IR. This is useful in multiprocessor applications.

The first breakpoint unit is programmed in the OCR using the BS and BE bits. The second breakpoint unit is programmed by the OnCE breakpoint 2 control (OBCTL2) register, located within the second breakpoint unit. The manner in which the two breakpoints are set up for generating triggers and interrupt conditions is specified by the BK bits in the OCR. The action which is performed when a final trigger is detected is specified by the EM bits in the OCR.