OnCE™ Module

12.4.6.3 Trace Occurrence (TO)—Bit 2

The read-only trace occurrence (TO) status bit is set when a trace event occurs. This bit is cleared by hardware reset if ENABLE_ONCE is not decoded in the JTAG IR and also by event rearm conditions described in Section 12.4.4.6, “Event Modifier (EM[1:0])—Bits 6–5.”

12.4.6.4 Hardware Breakpoint Occurrence (HBO)—Bit 1

The read-only hardware breakpoint occurrence (HBO) status bit is set when a OnCE hardware breakpoint event occurs. This bit is cleared by hardware reset if ENABLE_ONCE is not decoded in the JTAG IR and also by the event rearm conditions described in Section 12.4.4.6, “Event Modifier (EM[1:0])—Bits 6–5.” See Section 12.4.4.3, “Breakpoint Configuration (BK[4:0])—Bits 13–9,” to determine which encodings are defined to generate hardware breakpoint events.

12.4.6.5 Software Breakpoint Occurrence (SBO)—Bit 0

The read-only software breakpoint occurrence (SBO) status bit is set when a DSP DEBUG instruction is executed (for example, a software breakpoint event) except when PWD = 1 in the OCR.The SBO bit is cleared by hardware reset provided that ENABLE_ONCE is not decoded in the JTAG IR. It is also cleared by the event rearm conditions described in Section 12.4.4.6, “Event Modifier (EM[1:0])—Bits 6–5.” The EM[1:0] bits determine if the core or the FIFO is halted.

12.5 Breakpoint and Trace Registers

Section 12.5.1, “OnCE Breakpoint/Trace Counter Register (OCNTR),” through Section 12.5.5, “OnCE Breakpoint and Trace Section,” describe these OnCE breakpoint and trace registers:

•OnCE breakpoint/trace counter register (OCNTR)

•OnCE memory address latch (OMAL) register

•OnCE breakpoint address register (OBAR)

•OnCE memory address comparator (OMAC)

12.5.1 OnCE Breakpoint/Trace Counter Register (OCNTR)

The OnCE breakpoint/trace counter register (OCNTR) is an 8-bit counter that allows for as many as 256 valid address compares or instruction executions (depending on whether it is configured as a breakpoint or trace counter) to occur before a OnCE event occurs. In its most common use, OCNTR is $00 and the first valid address compare or instruction execution halts the core. If the user prefers to generate a OnCE event on n valid address compares or n instructions, OCNTR is loaded with n – 1. Again, if trace mode is selected and EM[1:0] is not cleared, only n – 1 instructions must execute before an event occurs.

When used as a breakpoint counter, the OCNTR becomes a powerful tool to debug real-time interrupt sequences such as servicing an A/D or D/A converter or stopping after a specific number of transfers from a peripheral have occurred. OCNTR is cleared by hardware reset provided that ENABLE_ONCE is not decoded in the JTAG IR.

When used as a trace mode counter, the OCNTR allows the user to single step through code, meaning that after each DSP instruction is executed, debug mode is reentered, allowing for display of the processor state after each instruction. By placing larger values in OCNTR, multiple instructions can be executed at full core speed before reentering debug mode. Trace mode is most useful when the EM bits are set for debug

Breakpoint and Trace Registers

mode entry, but the user has the ability to halt the FIFO or auto rearm the events (with a DE toggle). The trace feature helps the software developer debug sections of code that do not have a normal flow or are getting hung up in infinite loops. Using the trace counter also enables the user to debug areas of code that are time critical.

It is important to note that the breakpoint/trace logic is only enabled for instructions executed outside of debug mode. Instructions forced into the pipeline via the OnCE module do not cause trace or breakpoint events.

12.5.2 OnCE Memory Address Latch (OMAL) Register

The OnCE memory address latch (OMAL) register is a 16-bit register that latches the PAB or XAB1 on every cycle. This latching is disabled if the OnCE module is powered down with the OCR’s PWD bit.

NOTE:

The OMAL register does not latch the XAB2 bus. As a result, it is not possible to set an address breakpoint on any access done on the XAB2/XDB2 bus pair used for the second read in any dual read instruction.

12.5.3 OnCE Breakpoint Address Register (OBAR)

The OnCE breakpoint address register (OBAR) is a 16-bit OnCE register that stores the memory breakpoint address. OBAR is available for write operations only through the JTAG/OnCE serial interface. Before enabling breakpoints (by writing to OCR), OBAR should be written with its proper value. OBAR is for breakpoint 1 only and has no effect on breakpoint 2.

12.5.4 OnCE Memory Address Comparator (OMAC)

The OnCE memory address comparator (OMAC) is a 16-bit comparator that compares the current memory address (stored by OMAL) with the memory address register (OBAR). If OMAC is equal to OMAL, then the comparator delivers a signal indicating that the breakpoint address has been reached.

12.5.5 OnCE Breakpoint and Trace Section

Two capabilities useful for real-time debugging of embedded control applications are address breakpoints and full-speed instruction tracing. Traditionally, processors had set a breakpoint in program memory by replacing the instruction at the breakpoint address with an illegal instruction that causes a breakpoint exception. This technique is limiting in that breakpoints can only be set in RAM at the beginning of an opcode and not on an operand. In addition, this technique does not allow breakpoints to be set on data memory locations. The DSP56824 instead provides on-chip address comparison hardware for setting breakpoints on program or data memory accesses. This allows breakpoints to be set on program ROM as well as program RAM locations. Breakpoints can be programmed for reads, writes, program fetches, or memory accesses using the OCR’s BS and BE bits. See Section 12.4.4.8, “Breakpoint Selection (BS[1:0])—Bits 3–2.”