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Signal Descriptions

Table 2-4. Clock and Phase Lock Loop (PLL) Signals (Continued)

Signal Name

Signal

State During

Signal Description

Type

Reset

 

 

 

 

 

 

 

 

 

 

SXFC

Input

Input

External Filter Capacitor— This pin is used to add an external fil-

 

 

 

ter circuit to the PLL.

 

 

 

 

2.3

External Memory Interface (Port A)

 

 

 

 

 

Table 2-5. Address Bus Signals

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Signal

State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Signal Name

During

 

 

 

 

Signal Description

Type

 

 

 

 

 

 

 

 

Reset

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A0–A15

Output

Tri-stated

Address Bus— Signals A0–A15 change in T0 and specify the

 

 

 

 

 

 

 

address for an external program or data memory access. The value

 

 

 

 

 

 

 

of the DRV bit in the bus control register (BCR) causes the address

 

 

 

 

 

 

 

bus to retain the last external address (DRV = 1) or to be tri-stated

 

 

 

 

 

 

 

(DRV = 0) during an internal access or in stop or wait mode. See

 

 

 

 

 

 

 

Section 4.2.1, “Bus Control Register (BCR),” on page 4-3.

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 2-6. Data Bus Signals

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Signal

State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Signal Name

During

 

 

 

 

Signal Description

Type

 

 

 

 

 

 

 

 

Reset

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D0–D15

Input/

Tri-stated

Data Bus— Read data is sampled in on the trailing edge of T2, while

 

 

 

 

output

 

 

write data output is enabled on the leading edge of T2 and tri-stated

 

 

 

 

 

 

 

on the leading edge of T0. D0–D15 are tri-stated when the external

 

 

 

 

 

 

 

bus is inactive.

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 2-7. Bus Control Signals

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Signal

State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Signal Name

During

 

 

 

 

Signal Description

Type

 

 

 

 

 

 

 

 

Reset

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Output

Pulled

 

Program Memory Select

 

 

is asserted low for external program

 

PS

PS

 

 

 

 

 

high

 

memory access. If the external bus is not used during an instruction

 

 

 

 

 

internally

 

cycle (T0, T1, T2, or T3),

PS

is deasserted high in T0. During an

 

 

 

 

 

 

 

internal access in stop or wait mode, the value of the DRV bit in the

 

 

 

 

 

 

 

BCR determines whether the chip continues to drive

PS

(DRV = 1)

 

 

 

 

 

 

 

or tri-states

PS

(DRV = 0).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Output

Pulled

 

Data Memory Select

 

 

 

is asserted low during T0 for external

 

DS

DS

 

 

 

 

 

high

 

data memory access. If the external bus is not accessed during an

 

 

 

 

 

internally

 

instruction cycle (T0, T1, T2, or T3),

DS

is deasserted high in T0.

 

 

 

 

 

 

 

During an internal access in stop or wait mode, the value of the

 

 

 

 

 

 

 

DRV bit in the BCR determines whether the chip continues to drive

 

 

 

 

 

 

 

DS

(DRV = 1) or tri-states

DS

(DRV = 0).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2-4

DSP56824 User’s Manual

 

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