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OnCE™ Module

 

 

 

Table 12-7. R/W Bit Definition

 

 

 

 

 

 

Action

R/W

 

 

 

 

 

 

 

0

 

Write to the register specified by the RS[4:0] bits

 

 

 

1

 

Read from the register specified by the RS[4:0] bits

 

 

 

 

12.4.3 OnCE Decoder (ODEC)

The OnCE decoder (ODEC) decodes all OnCE instructions received in the OCMDR. The ODEC generates all the strobes required for reading and writing the selected OnCE registers. This block prohibits access to the OnCE program data bus register (OPDBR) and the OnCE PGDB bus transfer register (OPGDBR) if the chip is not in debug mode. Accessing the program address bus (PAB) pipeline registers from user mode when the FIFO is not halted gives indeterminate results. The ODEC works closely with the OnCE state machine on register reads and writes.

12.4.4 OnCE Control Register (OCR)

The 16-bit OnCE control register (OCR) contains bit fields that determine how breakpoints are triggered and what action occurs when a OnCE event occurs, and it also controls other miscellaneous OnCE features. Figure 12-7 illustrates the OCR and its fields.

OCR— $02

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

OnCE Control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

COP

DE

BK

BK

BK

BK

BK

DRM

FH

EM1

EM0

PWD

BS1

BS0

BE1

 

BE0

 

Register

 

 

OnCE Reset = $0010

DIS

 

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

Read/Write

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AA0107

Figure 12-7. OCR Programming Model

12.4.4.1 COP Timer Disable (COPDIS)—Bit 15

The COP timer disable (COPDIS) bit is used to prevent the COP timer from resetting the DSP chip when it times out. When COPDIS is cleared, the COP timer is enabled. When COPDIS is set, the COP timer is disabled.

NOTE:

When the COP enable (CPE) bit in the COP/RTI control (COPCTL) register is cleared, the COP timer is not enabled. In this case, the COPDIS bit has no effect on the deactivated COP timer. (No COP reset can be generated.) However, the COPDIS bit overrides the CPE bit when both are set. See Section 11.2.1.1, “COP Enable (CPE)—Bit 15,” on page 11-4 for more information.

12.4.4.2 DE Pin Output Enable (DE)—Bit 14

The DE pin enable (DE) bit configures the TRST/DE pin as an output. When DE is set, the TRST capability is disabled. When DE is cleared, the pin is configured as the TRST input. To avoid the accidental reset of JTAG, the user should change DE only when DRM = 1. DE and DRM should not be changed simultaneously. See Section 12.4.4.4, “Debug Request Mask (DRM)—Bit 8,” for details on how DE and DRM bits control TRST/DE functionality.

12-14

DSP56824 User’s Manual

 

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