OnCE™ Module

12.4 Command, Status, and Control Registers

The OnCE command, status, and control registers are described in Section 12.4.1, “OnCE Shift Register (OSHR),” through Section 12.4.6, “OnCE Status Register (OSR).” They include these registers:

•OnCE shift register (OSHR)

•OnCE command register (OCMDR)

•OnCE decoder (ODEC) register

•OnCE control register (OCR)

•OnCE breakpoint 2 control (OBCTL2) register

•OnCE status register (OSR)

12.4.1 OnCE Shift Register (OSHR)

The OnCE shift register (OSHR) is a JTAG shift register that samples the TDI pin on the rising edge of TCK in Shift-DR and provides output to the TDO pin on the falling edge of TCK. During OCMDR and OSR transfers, this register is 8 bits wide. During all other transfers, this register is 16 bits wide. The input from TDI is clocked first into the MSB of the OSHR. The TDO pin receives data from the least significant bit (LSB) of the OSHR.

12.4.2 OnCE Command Register (OCMDR)

The OnCE module has its own instruction register and instruction decoder, the OnCE command register (OCMDR). After a command is latched into the OCMDR, the command decoder implements the instruction through the OnCE state machine and control block. There are two types of commands: read commands that cause the chip to deliver required data, and write commands that transfer data into the chip and write it in one of the on-chip resources. The commands are 8 bits long and have the format shown in Figure 12-6. The lowest 5 bits (RS[4:0]) identify the source for the operation, defined in Table 12-4. Bits 5, 6, and 7 define the exit (EX) command bit (Table 12-5 on page 12-13), the execute (GO) bit (Table 12-6 on page 12-13), and the read/write (R/W) bit (Table 12-7 on page 12-14), respectively.

Command, Status, and Control Registers

Table 12-4. Register Select Encoding (Continued)

0Remain in the debug processing state

1Leave the debug processing state

Note: Bit 5 in the OnCE command word is the exit command. To leave debug mode and reenter the normal mode, both the EX and GO bits must be asserted in the OnCE input command register.