OnCE™ Module
12.3.2 OnCE Programming Model
The programming model for the OnCE port consists of the registers which control all emulation and debugging tasks. These consist of command, status, and control registers, as well as breakpoint and bus status registers. The registers in the OnCE port programming model are shown in Figure 12-3 and Figure 12-4.
OCMDR |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
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OnCE Command |
R/W |
GO |
EX |
RS4 |
RS3 |
RS2 |
RS1 |
RS0 |
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Reset: Not modified |
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Write-Only |
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OSR |
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6 |
5 |
4 |
3 |
2 |
1 |
0 |
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OnCE Status |
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Register |
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OS1 |
OS0 |
TO |
HBO |
SBO |
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OnCE Reset* = $00 |
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Read-Only |
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OCR— $02 |
15 |
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10 |
9 |
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5 |
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3 |
2 |
1 |
0 |
OnCE Control |
COP |
DE |
BK |
BK |
BK |
BK |
BK |
DRM |
FH |
EM1 |
EM0 |
PWD |
BS1 |
BS0 |
BE1 |
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OnCE Reset = $0010 |
DIS |
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3 |
2 |
1 |
0 |
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Read/Write |
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OCNTR— $03 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
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OnCE Count |
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8-bit event counter |
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Register |
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OnCE Reset = $0000 |
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Read/Write |
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OBAR— $04 15 14 |
13 12 11 10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
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OnCE Breakpoint |
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16-bit breakpoint address register |
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Address Register |
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Reset: Not modified |
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(program or data memory breakpoints) |
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Write-Only |
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* Indicates reserved bits, written as zero for future compatibility |
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OnCE reset occurs when hardware or COP reset occurs, and an ENABLE_ONCE instruction |
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is not latched into the JTAG instruction register (IR) |
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AA1389A |
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Figure 12-3. OnCE Module Registers Accessed Through JTAG
12-6 |
DSP56824 User’s Manual |
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OnCE Module Architecture
OPGDBR— $08 |
15 14 13 12 11 10 9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
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OnCE PGDB |
16-bit register used to read registers and memory values |
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Register |
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from the DSP core |
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Reset: Not modified |
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Read-Only |
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OPDBR— $09 |
15 |
14 |
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0 |
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OnCE PDB |
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16-bit register used to execute instructions in debug mode |
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Register |
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and restore pipeline upon exit |
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Reset: Not modified |
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Read/Write |
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OPABFR— $0A |
15 |
14 |
13 |
12 |
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10 |
9 |
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0 |
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OnCE PAB |
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16-bit program fetch address |
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Fetch Register |
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Reset: Not modified |
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Read-Only |
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OPABER— $10 |
15 14 13 12 11 10 9 |
8 |
7 |
6 |
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3 |
2 |
1 |
0 |
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OnCE PAB |
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16-bit program execute address |
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Execute Register |
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Reset: Not modified |
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Read-Only |
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OPABDR— $13 |
15 |
14 |
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12 |
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10 |
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2 |
1 |
0 |
OnCE PAB |
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16-bit program decode address |
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Decode Register |
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Reset: Not modified |
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Read-Only |
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AA1389B
Figure 12-3. OnCE Module Registers Accessed Through JTAG (Continued)
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OnCE™ Module |
12-7 |
OnCE™ Module
OBAR2— $05 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
OnCE Breakpoint |
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16-bit breakpoint address register |
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Address Register 2 |
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(address or data breakpoints) |
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Reset: Not modified |
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Read/Write |
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OBMSK2— $06 |
15 |
14 |
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12 |
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10 |
9 |
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0 |
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OnCE Breakpoint |
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16-bit breakpoint mask register |
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Mask Register 2 |
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(address or data breakpoints) |
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Reset: Not modified |
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Read/Write |
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OBCTL2— $07 |
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OnCE Breakpoint |
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EN |
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INV |
DAT |
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Control Register 2 |
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OnCE Reset = $0 |
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Read/Write |
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OnCE reset occurs when hardware or Computer Operating Properly (COP) reset occurs, and an ENABLE_ONCE instruction |
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is not latched into the JTAG port instruction register (IR) |
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AA1389C |
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Figure 12-3. OnCE Module Registers Accessed Through JTAG (Continued) |
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OPGDBR— X:$FFFF |
15 |
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0 |
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OnCE PGDB |
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16-bit register used to read registers and memory values |
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Register |
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from the DSP core |
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Reset: Not modified |
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Write-Only |
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OPDBR |
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15 |
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9 |
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OnCE PDB |
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Register |
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16-bit register used to execute instructions in debug mode |
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Reset: Not modified |
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and restore pipeline upon exit |
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Write-Only |
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OnCE Port interrupt vector:
OnCE TRAP |
P:$000C |
OnCE TRAPs are Level 1 interrupts and not programmable in the IPR
Note: OPGDBR and OPDBR are not dedicated OnCE module registers. They share functionality with the core. If used
incorrectly, they can give unexpected results.
AA1390
Figure 12-4. OnCE Module Registers Accessed from the Core
The OnCE module has an associated interrupt vector $000C. The user can configure the event modifier (EM) bits of the OCR such that a OnCE event other than trace generates a level 1 non-maskable interrupt. This interrupt capability is described in Section 12.4.4.6, “Event Modifier (EM[1:0])—Bits 6–5.”
12-8 |
DSP56824 User’s Manual |
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