JTAG/OnCE Port Pinout
12.2 JTAG/OnCE Port Pinout
As described in the IEEE 1149.1a-1993 specification, the JTAG port requires a minimum of four pins to support TDI, TDO, TCK, and TMS signals. The DSP56824 also uses the optional test reset (TRST) input signal and multiplexes it so that the same pin can support the debug event (DE) output signal used by the OnCE interface. The pin functions are described in Table 12-1.
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Table 12-1. JTAG/OnCE Pin Descriptions |
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Pin Name |
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Pin Description |
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TDI |
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Test Data Input— This input provides a serial data stream to the JTAG and the OnCE module. It is |
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sampled on the rising edge of TCK and has an on-chip pull-up resistor. |
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TDO |
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Test Data Output— This tri-statable output provides a serial data stream from the JTAG and the OnCE |
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module. It is driven in the Shift-IR and Shift-DR controller states of the JTAG state machine and changes |
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on the falling edge of TCK. |
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TCK |
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Test Clock Input— This input provides a gated clock to synchronize the test logic and shift serial data |
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through the JTAG/OnCE port. The maximum frequency for TCK is one-eighth the maximum frequency |
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of the DSP56824 (that is, 5 MHz for TCK if the maximum CLK input is 40 MHz). The TCK pin has an |
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on-chip pull-down resistor. |
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TMS |
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Test Mode Select Input— This input sequences the TAP controller’s state machine. It is sampled on |
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the rising edge of TCK and has an on-chip pull-up resistor. |
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Test Reset/Debug Event— This bidirectional pin, when configured as an input, provides a reset signal |
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TRST |
DE |
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to the TAP controller. When configured as an output, it signals debug events detected on a trigger condi- |
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tion. Pin operation is configured by bit 14 of the OnCE control register (OCR). The |
TRST |
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DE |
pin has an |
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on-chip pull-up resistor. |
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The TRST/DE pin can be configured for one of two functions. It can be used as a reset for the JTAG port or can provide a useful event-acknowledge feature. This selection is performed through appropriate control bits in the OCR. The two functions available are as follows:
•TRST—When enabled, this input resets the JTAG TAP controller state machine.
•DE—When enabled, this open-drain output provides a signal that indicates that an event has occurred in the OnCE debug logic. This event can be any of the following occurrences:
—Hardware breakpoint
—Software breakpoint
—Trace or entry into debug mode caused by a DEBUG_REQUEST instruction being decoded in the JTAG port instruction register (IR)
Events cause TRST/DE to be asserted only if DE = 1 and DRM = 0 (in the OCR), as shown in Table 12-2.
Table 12-2. DE and DRM Encoding for TRST/DE Assertion
DE |
DRM |
Function |
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0 |
X |
Input: JTAG reset when |
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pulled low |
TRST |
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1 |
0 |
Output: pulled low on OnCE events |
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1 |
1 |
Output: disabled (weak on-chip pull-up) |
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OnCE™ Module |
12-3 |