2.1 Power and Ground Signals

Table 2-2. Power Inputs

Signal Name

Signal Description

(Number of Pins)

VDD (9)

Power— These pins provide power to the internal structures of the chip, and should all be

attached to VDD.

VDDPLL (1)

PLL Power— This pin supplies a quiet power source to the VCO to provide greater fre-

quency stability.

Table 2-3. Grounds

Signal Name

Signal Description

(Number of Pins)

VSS (9)

GND— These pins provide grounding for the internal structures of the chip and should all

be attached to VSS.

VSSPLL (1)

PLL Ground— This pin supplies a quiet ground to the VCO to provide greater frequency

stability.

Signal Name

Signal

State During

Signal Description

Type

Reset

EXTAL

Input

Input

External Clock/Crystal Input— This input should be connected to

an external clock or to an external oscillator. After being squared,

the input clock can be selected to provide the clock directly to the

DSP core. The minimum instruction time is two input clock periods

broken up into four phases named T0, T1, T2, and T3. This input

clock can also be selected as the input clock for the on-chip PLL.

When the low frequency mode of

is selected, EXTAL is in

XCOLF

phase with Phi1, T1, and T3. When the default mode is selected,

EXTAL is in phase with CLKO, Phi0, T0, and T2.

XTAL

Output

Chip-driven

Crystal Output— This output connects the internal crystal oscillator

output to an external crystal. If an external clock is used, XTAL

should not be connected.

CLKO

Output

Chip-driven

Clock Output— This pin outputs a buffered clock signal. By program-

ming the CS[1:0] bits in the PLL control register 1 (PCR1), the user

can select between outputting a squared version of the signal applied

to EXTAL and a version of the DSP master clock at the output of the

PLL. The clock frequency on this pin can also be disabled by program-

ming the CS[1:0] bits in PCR1.

Signal Descriptions

2-3