- •Table of Contents
- •Part 1 Overview
- •1.1 Data Sheet Conventions
- •1.2 DSP56824 Features
- •1.2.1 Digital Signal Processing Core
- •1.2.2 Memory
- •1.2.3 Peripheral Circuits
- •1.2.4 Energy Efficient Design
- •1.3 Product Documentation
- •1.4 For the Latest Information
- •Part 2 Signal/Connection Descriptions
- •2.1 Introduction
- •2.2 Power and Ground Signals
- •2.3 Clock and Phase Lock Loop Signals
- •2.4 Address, Data, and Bus Control Signals
- •2.5 Interrupt and Mode Control Signals
- •2.6 GPIO Signals
- •2.7 Serial Peripheral Interface (SPI) Signals
- •2.8 Synchronous Serial Interface (SSI) Signals
- •2.9 Timer Module Signals
- •2.10 JTAG/OnCE™ Port Signals
- •Part 3 Specifications
- •3.1 General Characteristics
- •3.2 DC Electrical Characteristics
- •3.3 AC Electrical Characteristics
- •3.4 External Clock Operation
- •3.5 External Components for the PLL
- •3.6 Port A External Bus Synchronous Timing
- •3.6.1 Capacitance Derating
- •3.7 Port A External Bus Asynchronous Timing
- •3.9 Port B and C Pin GPIO Timing
- •3.10 Serial Peripheral Interface (SPI) Timing
- •3.11 Synchronous Serial Interface (SSI) Timing
- •3.12 Timer Timing
- •3.13 JTAG Timing
- •Part 4 Packaging
- •4.1 Package and Pin-Out Information
- •4.2 Ordering Drawings
- •Part 5 Design Considerations
- •5.1 Thermal Design Considerations
- •5.2 Electrical Design Considerations
- •Part 6 Ordering Information
Part 1 Overview
16 to 32 GPIO lines
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8 |
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Serial |
Synch. |
Timer/ |
COP/ |
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mable |
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Periph. |
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Serial |
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Memory |
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Memory |
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PLL Interrupt |
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Interface |
Interface |
Interface |
Counters |
RTI |
32 K × |
16 ROM |
3584 × |
2048 × |
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128 × |
16 RAM |
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16 ROM |
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or GPIO |
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PAB |
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DSP56800 |
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XAB2 |
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PGDB |
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XDB2 |
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PDB |
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CGDB |
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JTAG/ |
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Data ALU |
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36-bit MAC |
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Three 16-bit Input Registers |
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MODA/IRQA |
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RESET |
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AA1445 |
Figure 1. DSP56824 Block Diagram
DSP56824 Technical Data |
3 |
1.1 Data Sheet Conventions
This document uses the following conventions:
•OVERBAR is used to indicate a signal that is active when pulled low: for example, RESET.
•Logic level one is a voltage that corresponds to Boolean true (1) state.
•Logic level zero is a voltage that corresponds to Boolean false (0) state.
•To set a bit or bits means to establish logic level one.
•To clear a bit or bits means to establish logic level zero.
•A signal is an electronic construct whose state or changes in state convey information.
•A pin is an external physical connection. The same pin can be used to connect a number of signals.
•Asserted means that a discrete signal is in active logic state.
—Active low signals change from logic level one to logic level zero.
—Active high signals change from logic level zero to logic level one.
•Deasserted means that an asserted discrete signal changes logic state.
—Active low signals change from logic level zero to logic level one.
—Active high signals change from logic level on to logic level zero.
•LSB means least significant bit or bits. MSB means most significant bit or bits. References to low and high bytes or words are spelled out.
Please refer to the examples in Table 1.
Table 1. Data Conventions
Signal/Symbol |
Logic State |
Signal State |
Voltage |
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True |
Asserted |
VIL/VOL |
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False |
Deasserted |
VIH/VOH |
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True |
Asserted |
VIH/VOH |
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False |
Deasserted |
VIL/VOL |
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4 |
DSP56824 Technical Data |
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