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Поволжский государственный технологический университет

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ЦОС_Заочники2013 / Курсовая МПиЦОС 2011 / Справочная информация / Моторола / DSP568xx / dsp56824.pdf

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IRQA

A0–A15,

PS, DS,

RD, WR

First Instruction Fetch

Not IRQA Interrupt Vector

AA0192

Figure 19. Recovery from Stop State Using Asynchronous Interrupt Timing

IRQA

A0–A15

PS, DS,

RD, WR

First IRQA Interrupt

Instruction Fetch

AA0193

Figure 20. Recovery from Stop State Using IRQA Interrupt Service

3.9 Port B and C Pin GPIO Timing

(VSS = 0 V, VDD = 2.7–3.6 V, TA = –40° to +85° C, CL = 50 pF)

Table 27. GPIO Timing

No.	Characteristics		Min1	Max1	Unit


80	CLKO high to GPIO out valid (GPIO out delay time)	2	—	10.7	ns
	CLKO high to GPIO out valid (GPIO out delay time)

81	CLKO high to GPIO out not valid (GPIO out hold time)		1.5	—	ns

82	GPIO in valid to CLKO high (GPIO in set-up time)		7.8	—	ns

83	CLKO high to GPIO in not valid (GPIO in hold time)		0.5	—	ns

84	Fetch to CLKO high before GPIO change		12T – 1.7	—	ns

DSP56824 Technical Data

Port B and C Pin GPIO Timing

Table 27. GPIO Timing (Continued)

No.	Characteristics	Min1	Max1	Unit

85	Port B interrupt pulse width	4T	—	ns

86	Port B interrupt assertion to external data memory access out
	valid, caused by first instruction execution in the interrupt service	19T + 9.6	—	ns
	routine

87	Port B interrupt assertion to general purpose output valid, caused
	by first instruction execution in the interrupt service routine	31T + 10.	—	ns
		8

1.In the formulas, T = 1/2 the clock cycle. For an internal frequency of 70 MHz, T = 7.14 ns.

2.If a 10 kW pullup or pulldown resistor is connected to XCOLF/PB15, add 3.9 ns for timings on XCOLF/PB15.

	CLKO
	(Output)
		80
		81
	GPIO
	(Output)
		82
		83
	GPIO	VALID
	(Input)	VALID
	(Input)

A0–A15

Fetch the instruction MOVE X0,X:(R0); X0 contains the new value of GPIO

and R0 contains the address of GPIO data register.

AA0194

Figure 21. GPIO Timing

Port B
GPIO
Interrupt
(Input)	85
	85

AA0195

Figure 22. Port B Interrupt Timing (Negative-Edge-Sensitive)

DSP56824 Technical Data

A0–A15,

PS, DS,

First Interrupt Instruction Execution

RD, WR

Port B

GPIO

Interrupt

(Input)

a) First Interrupt Instruction Execution

General

Purpose

I/O Pin

Port B

GPIO Interrupt (Input)

b) General Purpose I/O

AA0196

Figure 23. Port B GPIO Interrupt Timing

3.10 Serial Peripheral Interface (SPI) Timing

	(VSS = 0 V, VDD = 2.7–3.6 V, TA = –40°		to +85° C)
		Table 28. SPI Timing

					70 MHz

	No.	Characteristic		20 pF Output Load		50 pF Output Load		Unit

				Min	Max	Min	Max


90		Cycle time
		Master		100	—	100	—	ns
		Slave		100	—	100	—	ns

91		Enable lead time
		Master		—	—	—	—	ns
		Slave		6.8	—	25	—	ns

92		Enable lag time
		Master		—	—	—	—	ns
		Slave		6.5	—	100	—	ns

93		Clock (SCK) high time						ns
		Master		17.6	—	17.6	—	ns
		Slave		25	—	25	—

94		Clock (SCK) low time
		Master		24.1	—	24.1	—	ns
		Slave		25	—	25	—	ns

DSP56824 Technical Data

Serial Peripheral Interface (SPI) Timing

Table 28. SPI Timing (Continued)

			70 MHz

No.	Characteristic	20 pF Output Load		50 pF Output Load		Unit

		Min	Max	Min	Max

95	Data setup time (inputs)
	Master	15.6	—	20	—	ns
	Slave	–3.2	—	0	—	ns

96	Data hold time (inputs)
	Master	0	—	0	—	ns
	Slave	0	—	0	—	ns

97	Access time (time to data active from
	high-impedance state)					ns
	Slave	4.8	10.7	4.8	15	ns

98	Disable time (hold time to high-
	impedance state)					ns
	Slave	3.7	15.2	3.7	15.2	ns

99	Data Valid
	Master	4.5	3.5	4.5	3.5	ns
	Slave (after enable edge)	4.6	20.4	4.6	20.4	ns


100	Data invalid
	Master	0	—	0	—	ns
	Slave	0	—	0	—	ns

101	Rise time
	Master	4.1	5.5	4.1	11.5	ns
	Slave	0	4.0	0	10.0	ns

102	Fall time
	Master	1.5	4.7	2.0	9.7	ns
	Slave	0	4.0	2.0	9.0	ns

DSP56824 Technical Data

	SS
	SS		SS is held High on master
(Input)			SS is held High on master
(Input)
		90

				101
SCK (CPL = 0)			94		102
SCK (CPL = 0)	See
(Output)	Note
		93		102
				102
		94			101
		94
SCK (CPL = 1)	See
(Output)	Note
		96	93
	95		93
	95
MISO		MSB in	Bits 6–1		LSB in
(Input)		MSB in	Bits 6–1		LSB in
(Input)
	99 (ref)	100		99	100 (ref)
	99 (ref)	100

MOSI

Master MSB out

Bits 6–1

Master LSB out

(Output)

102

101

Note:

This first clock edge is generated internally, but is not seen at the SCK pin.

AA0197

Figure 24. SPI Master Timing (CPH = 0)

DSP56824 Technical Data

Serial Peripheral Interface (SPI) Timing


	SS
	SS	SS is held High on master
(Input)		SS is held High on master
(Input)

	90		102
			102
	94			101
SCK (CPL = 0)				See
(Output)				Note
	93			102
				102
	94
SCK (CPL = 1)				See
(Output)				Note
	93			95
		101		95
		101		96
				96
MISO	MSB in	Bits 6–1		LSB in
(Input)	MSB in	Bits 6–1		LSB in
(Input)
99 (ref)	100		99	100(ref)
99 (ref)	100

MOSI

Master MSB out

Bits 6 – 1

Master LSB out

(Output)

102

101

Note:

This last clock edge is generated internally, but is not seen at the SCK pin.

AA0198

Figure 25. SPI Master Timing (CPH = 1)

DSP56824 Technical Data

SS
(Input)
		90		102	92
					92
SCK (CPL = 0)		94		101
SCK (CPL = 0)
(Input)
	93
	91
	94
SCK (CPL = 1)
(Input)
	97	93	101		102	98
	97	93	101

MISO	Slave MSB out		Bits 6–1	Slave LSB out		See
(Output)	Slave MSB out		Bits 6–1	Slave LSB out		Note
(Output)						Note
	95		99	100		100
		96		100		100
		96

MOSI

MSB in

Bits 6–1

LSB in

(Input)

Note:

Not defined, but normally MSB of character just received

AA0199

Figure 26. SPI Slave Timing (CPH = 0)

DSP56824 Technical Data

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