Core Architecture Overview

2.3.2 Program Memory

Program memory (program RAM, program ROM, or both) can be added around the core on a chip. Addresses are received from the PAB and data transfers occur on the PDB. The first 128 locations of the program memory are available for interrupt vectors, although it is not necessary to use all 128 locations for interrupt vectors. Some can be used for the user program if desired. The number of locations required for an application depends on what peripherals on the chip are used by an application and the locations of their corresponding interrupt vectors. The program memory may be expanded off chip, and up to 65,536 locations can be addressed.

2.3.3 Bootstrap Memory

A program bootstrap ROM is usually found on chips that have on-chip program RAM instead of ROM. The bootstrap ROM is used for initially loading application code into the on-chip program RAM so it can be run from there. Refer to Section 5.1.9.1, “Operating Mode Bits (MB and MA)—Bits 1–0,” on page 5-10 and to the user’s manual of the particular DSP chip for a description of the different bootstrapping modes.

2.3.4 IP-BUS Bridge

Some devices based on the DSP56800 architecture connect to on-chip peripherals using the Motorola-standard IP-BUS interface. These devices contain an IP-BUS bridge unit, which allows peripherals to be accessed using the CGDB data bus and XAB1 address bus. Peripheral registers are memory-mapped into the data address space. Consult the appropriate DSP56800-based device User’s Manual for more information on peripheral interfacing for a particular chip.

2.3.5 Phase Lock Loop (PLL)

The phase lock loop (PLL) allows the DSP chip to use an external clock different from the internal system clock, while optionally supplying an output clock synchronized to a synthesized internal clock. This PLL allows full-speed operation using an external clock running at a different speed. The PLL performs frequency multiplication, skew elimination, and reduces overall system power by reducing the frequency on the input reference clock.

2.4 DSP56800 Core Programming Model

The registers in the DSP56800 core that are considered part of the DSP56800 core programming model are shown in Figure 2-4 on page 2-9. There may also be other important registers that are not included in the DSP56800 core, but mapped into the data address space. These include registers for peripheral devices and other functions that are not bound into the core.

DSP56800 Core Programming Model

Data Arithmetic Logic Unit

Address Generation Unit

Program Controller Unit

AA0007

Figure 2-4. DSP56800 Core Programming Model

Core Architecture Overview

Chapter 3

Data Arithmetic Logic Unit

This chapter describes the architecture and the operation of the data arithmetic logic unit (ALU), the block where the multiplication, logical operations, and arithmetic operations are performed. (Addition can also be performed in the address generation unit, and the bit-manipulation unit can perform logical operations.) The data ALU contains the following:

•Three 16-bit input registers (X0, Y0, and Y1)

•Two 32-bit accumulator registers (A and B)

•Two 4-bit accumulator extension registers (A2 and B2)

•An accumulator shifter (AS)

•One data limiter

•One 16-bit barrel shifter

•One parallel (single cycle, non-pipelined) multiply-accumulator (MAC) unit

Multiple buses in the data ALU perform complex arithmetic operations (such as a multiply-accumulate operations) in parallel with up to two memory transfers. A discussion of fractional and integer data representations; signed, unsigned, and multi-precision arithmetic; condition code generation; and the rounding modes used in the data ALU are also described in this section.

The data ALU can perform the following operations in a single instruction cycle:

•Multiplication (with or without rounding)

•Multiplication with inverted product (with or without rounding)

•Multiplication and accumulation (with or without rounding)

•Multiplication and accumulation with inverted product (with or without rounding)

•Addition and subtraction

•Compares

•Increments and decrements

•Logical operations (AND, OR, and EOR)

•One’s-complement

•Two’s-complement (negation)

•Arithmetic and logical shifts

•Rotates

•Multi-bit shifts on 16-bit values

•Rounding

•Absolute value