A.4.2 Effects of the Operating Mode Register’s SA Bit

The SA bit in the Operating Mode Register (OMR) can affect the computation of certain condition code bits. This bit enables the MAC Output Limiter within the data ALU. When enabled, the results of many operations are limited to fit with 32 bits, the extension portion containing only sign information. This limiting operation has both direct and indirect effects on the way condition codes are computed.

The SA bit directly affects the following condition code bits:

•U—cleared if saturation occurs in the MAC Output Limiter

•V—set when saturation occurs in the MAC Output Limiter

The remaining bits in the Condition Code Register are not affected by the SA bit, with the following exceptions:

•L—may be indirectly affected through effects on the V bit

•N—affected only by the ASRAC, LSRAC, and IMPY instructions

•C—affected only by the ASL instruction

The value of the SA bit is designed not to affect condition code computation for the TSTW instructions. Only the U condition code bit is affected by the SA bit for the CMP instruction. These instructions operate independently of the CC bit and correctly generate both signed and unsigned condition codes.

The SA bit only affects operations in the data ALU, not operations performed in other blocks. These include move instructions, bit-manipulation instructions, and address calculations performed by the AGU.

NOTE:

When SA is set to one for an application, condition codes are not always set in an intuitive manner. It is best to examine the instruction details to determine the effect on condition codes when SA is one. See Section A.7, “Instruction Descriptions.”

A.4.3 Effects of the OMR’s CC Bit

The CC bit in the OMR may affect the computation of the condition code bits. The CC bit establishes how many of the bits of an arithmetic or logic operation result are used when calculating condition codes. Specifically:

•When CC = 0, the result is interpreted as 36 bits with a valid extension portion.

•When CC = 1, the result is interpreted as 32 bits with the extension portion ignored.

Signed values can be computed in both cases, but computation of unsigned values must be performed with the CC bit set to one. Without setting CC to one prior to executing the TST and CMP instructions, the HI, HS, LO, and LS branch/jump conditions cannot be used.

When the CC bit is set, the following condition code bits are affected:

•V—set based on the MSB of the result’s MSP portion

•Z—set using only the MSP and LSP portions of the result

The remaining bits in the Condition Code Register are not affected by the CC bit, with the following exceptions:

•L—may be indirectly affected through effects on the V bit

•N—affected only by the ASRAC, LSRAC, IMPY, and ASLL instructions

•C—affected only by the ASL instruction

The value of the CC bit does not affect condition code computation for the TSTW instructions. These instructions operate independently of the CC bit and correctly generate both signed and unsigned condition codes.

The CC bit only affects operations in the data ALU, not operations performed in other blocks. These include move instructions, bit-manipulation instructions, and address calculations performed by the AGU.

A.4.4 Condition Code Summary by Instruction

Table A-9 provides a detailed view of the condition codes affected by each instruction, and the circumstances under which each condition code is set or cleared. Table A-8 describes the notation used. Items in the “Notes” column of Table A-9 are explained immediately following the table on page A-15.

The condition code computation shown in Table A-9 may differ from that defined in the opcode descriptions; see Section A.7, “Instruction Descriptions.” This indicates that the standard definition may be used to generate the specific condition code result. For example, the Z flag computation for the CLR instruction is shown as the standard definition, while the opcode description indicates that the Z flag is always set. Table A-9 gives the chip implementation viewpoint, while the opcode descriptions give the user viewpoint.

The “Comments” column in the table is also used to report if any of the upper bits in the status register are modified. These are not status bits because they do not lie in the status portion of the status register, but rather in the control portion. Sometimes these bits are also affected by instructions. Examples include the interrupt mask bits, I1 and I0, and the looping bits, LF and NL (NL lies in the OMR register).

The following instruction mnemonics are not found in Table A-9: ANDC, EORC, NOTC and ORC. This is because each of these is an alias for another instruction and not an instruction in its own right. To determine condition code calculation for each of these, determine the instructions to which these mnemonics are mapped (see Section 6.5.1, “ANDC, EORC, ORC, and NOTC Aliases,” on page 6-12) and look at the condition code information for the corresponding real instructions.

Table A-9. Condition Code Summary

Table A-9. Condition Code Summary (Continued)

Table A-9. Condition Code Summary (Continued)

NOTES:

1.V is set if the MSB of the destination operand (bit 35 for an accumulator or bit 31 for the Y register) is changed as a result of the left shift; V is cleared otherwise.

2.C is set if the MSB of the source operand (bit 35 for an accumulator or bit 31 for the Y register) is set and is cleared otherwise.

3.C is set if bit 0 of the source operand is set and is cleared otherwise.

4.C is set if all bits specified by the mask are set and is cleared otherwise. Bits that are not set in the mask should be ignored. If a bit-field instruction is performed on the status register, all bits in this register selected by the bit field’s mask can be affected.

5.C is set if all bits specified by the mask are cleared and is cleared otherwise. Ignore bits that are not set in the mask. Note that if a bit-field instruction is performed on the status register, all bits in this register selected by the bit field’s mask can be affected.

6.C is set if the MSB of the result is cleared (bit 35 for an accumulator or bit 31 for the Y register). The C bit is cleared if the MSB of the result is set.

7.For the accumulators, C is set if bit 31 of the source operand is set and is cleared otherwise. For the Y1, Y0, and X0 registers, C is set if bit 15 of the source operand is set and is cleared otherwise.

8.For the accumulators, C is set if bit 16 of the source operand is set and is cleared otherwise. For the Y1, Y0, and X0 registers, C is set if bit 0 of the source operand is set and is cleared otherwise.