Figure 9-1. JTAG/OnCE Interface Block Diagram

As already noted, the JTAG module is the master. It enables interaction with the debug services provided by the OnCE, and its external serial interface is used by the OnCE port for sending and receiving debugging commands and data.

9.2 JTAG Port

Problems associated with testing high-density circuit boards have led to the development of a proposed standard under the sponsorship of the Test Technology Committee of IEEE and the Joint Test Action Group (JTAG). The resulting standard, called the IEEE Standard Test Access Port and Boundary-Scan Architecture, specifies industry-standard, in-circuit device testing and diagnosis. The DSP56800 family provides a dedicated test access port (TAP) that is fully compatible with this standard, commonly referred to as the “JTAG port.”

This section provides an overview of the capabilities of the JTAG port as implemented on the DSP56800. Information provided here is intended to supplement the supporting IEEE 1149.1a-1993 document, which outlines the internal details, applications, and overall methodology of the standard. Specific details on the implementation of the JTAG port for a given DSP56800-based device are provided in that device’s user’s manual.

JTAG Port

9.2.1 JTAG Capabilities

The DSP56800 JTAG port has the following capabilities:

•Performing boundary scan operations to test circuit-board electrical continuity

•Sampling the DSP56800-based device system pins during operation and transparently shifting out the result in the boundary scan register; preloading values to output pins prior to performing a boundary scan operation

•Querying identification information (manufacturer, part number, and version) from a DSP56800-based device

•Adding a weak pull-up device on all input signals to cause all open inputs to report a logic 1 and to force a predictable internal state while performing external boundary scan operations

•Disabling the output drive to pins during circuit-board testing

•Forcing test data onto the outputs of a DSP56800-based device

•Providing a means of accessing the OnCE controller and circuits to control a target system

•Providing a means of entering the debug mode of operation

•Bypassing the DSP56800 core for a given circuit-board test by effectively reducing the boundary scan register to a single cell

Section 9.2.2, “JTAG Port Architecture,” provides an overview of the port’s architecture and commands. For additional information on the JTAG port’s implementation and command set, see the appropriate DSP56800-based device’s user’s manual.

9.2.2 JTAG Port Architecture

The JTAG module consists of the logic necessary to support boundary scan testing as defined in the IEEE specification. Although tightly coupled to the DSP56800’s core logic, it is an independent module, and, when disabled, it is guaranteed to have no impact on the function of the core.

The JTAG port consists of the following components:

•Serial communications interface

•Command decoder and interpreter

•Boundary scan register

•ID register

These units, and the overall once port architecture, are shown in Figure 9-2 on page 9-4.