Core Architecture Overview

DSP56800-based devices that implement the PGDB peripheral data bus. Instruction word fetches occur simultaneously over the PDB. The bus structure supports general register-to-register moves, register-to-memory moves, and memory-to-register moves, and can transfer up to three 16-bit words in the same instruction cycle. Transfers between buses are accomplished in the bus and bit-manipulation unit. As a general rule, when any register less than 16 bits wide is read, the unused bits are read as zeros. Reserved and unused bits should always be written with zeros to insure future compatibility.

2.2 Memory Architecture

The DSP56800 has a dual Harvard memory architecture, with separate program and data memory spaces. Each address space supports up to 216 (65,536) memory words. Dedicated address and data buses for each address space allow for simultaneous accesses to both program memory and data memory. There is also a support for a second read-only data path to data memory. In DSP56800 Family devices that implement this second bus, it is possible to initiate two simultaneous data read operations, allowing for a total of three parallel memory accesses.

Figure 2-2. DSP56800 Memory Spaces

Locations $0 through $007F in the program memory space are available for reset and interrupt vectors. Peripheral registers are located in the data memory address space as memory-mapped registers. This peripheral space can be located anywhere in the data address space, although the address range $FFC0–$FFFF is frequently used because an addressing mode optimized for this region provides faster access; however, the location of the peripheral space is dependent on the specific system implementation of the DSP56800 core. See Section 4.2.4.3, “I/O Short Address (Direct Addressing): <pp>,” on page 4-23 for more information.