Software Techniques

;Software Looping

;Data ALU Register Used for Loop Count

;Software Looping

;AGU Register Used for Loop Count

;Software Looping

;Memory Location (one of first 64 XRAM locations) Used for Loop Count

;(instructions)

8.6.4 Nested Loops

This section gives recommendations for and a detailed discussion of nested loops.

8.6.4.1 Recommendations

For nested looping it is recommended that the innermost loop be a hardware DO loop when appropriate and that all outer loops be implemented as software loops. Even though it is possible to nest hardware DO loops, it is better to implement all outer loops using software looping techniques for two reasons:

1.The DSP56800 allows only two nested hardware DO loops.

2.The execution time of an outer hardware loop is comparable to the execution time of a software loop.

Likewise, there is little difference in code size between a software loop and an outer loop implemented using the hardware DO mechanism.

The hardware nesting capability of DO loops should instead be used for efficient interrupt servicing. It is recommended that the main program and all subroutines use no nested hardware DO loops. It is also recommended that software looping be used whenever there is a JSR instruction within a loop and the called subroutine requires the hardware DO loop mechanism. If these two rules are followed, then it can be guaranteed that no more than one hardware DO loop is active at a time. If this is the case, then the second HWS location is always available to ISRs for faster interrupt processing. This significantly reduces the amount of code required to free up and restore the hardware looping resources such as the HWS when entering and exiting an ISR, since it is already known upon entering the ISR that a HWS location is available.

If this technique is used, the ISRs should not themselves be interruptible, or, if they can be interrupted, then any ISR that can interrupt an ISR already in progress must save off one HWS location. See Section 8.12, “Freeing One Hardware Stack Location.”

The following code shows the recommended nesting technique:

Loops

; Nesting Loops Recommended Technique

MOVE #3,X:$0003 ; Set up loop count for outer loop ; (software loop)

OUTER

;(instructions)

INNER

;(instructions)

It would also be possible to use a data ALU or AGU register if more speed is needed.

An exception to the preceding recommendation for nesting loops is for the unique case where the innermost loop executes a single-word instruction. In this case it is possible to use a REP loop for the innermost loop and a hardware DO loop for the outermost loop. This is demonstrated in the following code:

;Nesting Loops Recommended Technique for Special Case of REP Loop Nested

;Within a Hardware DO Loop

;(instructions)

;(instructions)

MOVE A,X:(R0)+

LABEL

The REP loop may not be interrupted, however, so this technique may not be useful for large loop counts on the innermost loop if there are tight requirements for interrupt latency in an application. If this is the case, then the first example with a software outer loop and an inner DO loop may be appropriate.

8.6.4.2 Nested Hardware DO and REP Loops

Nesting of hardware DO loops is permitted on the DSP56800 architecture. However, it is not recommended that this technique be used for nesting loops within a program. Rather, it is recommended that the hardware nesting of DO loops be used to provide more efficient interrupt processing, as described in Section 8.6.4.1, “Recommendations.”

Since the HWS is two locations deep, it is possible to nest one DO loop within another DO loop. Furthermore, since the REP instruction does not use the HWS, it is possible to place a REP instruction within these two nested DO loops. The following code shows the maximum nesting of hardware loops allowed on the DSP56800 processor:

Software Techniques

; Hardware Nested Looping Example of the Maximum Depth Allowed

;

;(instructions)

;(instructions)

The HWS’s current depth can be determined by the NL and LF bits, as shown in Table 5-3, “Program RAM Operating Modes,” on page 5-11. From these bits it is possible to determine whether there are no loops currently in progress, a single loop, or two nested loops. Refer to Section 5.1.9.8, “Reserved OMR Bits—Bits 2, 7 and 9–14,” on page 5-13 for the values of these bits in these different conditions.

For nested DO loops, it is required that there be at least three instructions after the POP of the LA and LC registers and before the label of any outer loop. This requirement shows up in the preceding example as three NOPs but can be fulfilled by any other instructions.

Further hardware nesting is possible by saving the contents of the HWS and later restoring the stack on completion, as described in Section 8.13, “Multitasking and the Hardware Stack.”

8.6.4.3 Comparison of Outer Looping Techniques

A comparison of the execution overhead and extra code size of software and hardware outer loops shows that for loop nesting, it is just as efficient to nest in software (see Table 8-1). If a data ALU register or AGU register is available for use as the loop count, each loop executes one cycle faster than nesting loops in hardware. If there are no on-chip registers available for the loop counter, then the third technique can be used that uses one of the first 64 locations of X data memory. This technique executes one cycle slower per loop than nesting loops in hardware. Each of the software techniques also uses fewer instruction words.

Table 8-1 Outer Loop Performance Comparison

It is recommended that the nesting of hardware DO loops not be used for implementing nested loops. Instead, it is recommended that all outer loops in a nested looping scheme be implemented using software looping techniques. Likewise, it is recommended that software looping techniques be used when a loop contains a JSR and the called routine contains many instructions or contains a hardware DO loop.