Incrementing and Decrementing Operations

8.3 Incrementing and Decrementing Operations

Almost any piece of data can be incremented or decremented. This section summarizes the different increments and decrements available to both registers and memory locations. It is important to note the LEA instruction, which is used to increment or decrement AGU pointer registers. The TSTW instruction is also used for decrementing AGU pointer registers. This instruction is similar to LEA but also sets the condition codes, making it useful for program looping and other tasks. The LEA and TSTW instructions do not cause a pipeline dependency in the AGU (see Section 4.4, “Pipeline Dependencies,” on page 4-33). The TSTW instruction is not available for incrementing an AGU pointer or for decrementing the SP register.

; Different ways to increment on the DSP56800 core

The many different techniques available help to prevent registers from being destroyed. Otherwise, as found on other architectures, it is necessary to first move data to an accumulator to perform an increment.

8.4 Division

It is possible to perform fractional or integer division on the DSP56800 core. There are several questions to consider when implementing division on the DSP core:

•Are both operands always guaranteed to be positive?

•Are operands fractional or integer?

•Is only the quotient needed, or is the remainder needed as well?

•Will the calculated quotient fit in 16 bits in integer division?

•Are the operands signed or unsigned?

•How many bits of precision are in the dividend?

•What about overflow in fractional and integer division?

•Will there be “integer division” effects?

NOTE:

In a division equation, the “dividend” is the numerator, the “divisor” is the denominator, and the “quotient” is the result.

Software Techniques

Once all these questions have been answered, it is possible to select the appropriate division algorithm. The fractional algorithms support a 32-bit signed dividend, and the integer algorithms support a 31-bit signed dividend. All algorithms support a 16-bit divisor.

Note that the most general division algorithms are the fractional and integer algorithms for four-quadrant division that generate both a quotient and a remainder. These take the largest number of instruction cycles to complete and use the most registers.

For extended precision division, where the number of quotient bits required is more than 16, the DIV instruction and routines presented in this section are no longer applicable. For further information on division algorithms, consult the following references (or others as required):

Theory and Application of Digital Signal Processing, Lawrence R. Rabiner and Bernard Gold (Prentice-Hall: 1975), pages 524–530.

Computer Architecture and Organization, John Hayes (McGraw-Hill: 1978), pages 190–199.

8.4.1 Positive Dividend and Divisor with Remainder

The algorithms in the following code are the fastest and take the least amount of program memory. In order to use these algorithms, it must be guaranteed that both the dividend and divisor are both positive, signed, two’s-complement numbers. One algorithm is presented for the division of fractional numbers and a second is presented for the division of integer numbers. Both algorithms generate the correct positive quotient and positive remainder.

; Division of Fractional, Positive Data (B1:B0 / X0)

;in B0 and the positive remainder is in B1)

;Division of Integer, Positive Data (B1:B0 / X0)

Division

8.4.2 Signed Dividend and Divisor with No Remainder

The algorithms in the following code provide fast ways to divide two signed, two’s-complement numbers. These algorithms are faster because they generate the quotient only; they do not generate a correct remainder. The algorithms are referred to as four-quadrant division because they allow any combination of positive or negative operands for the dividend and divisor. One algorithm is presented for the division of fractional numbers, and a second is presented for the division of integer numbers.

;4 Quadrant Division of Fractional, Signed Data (B1:B0 / X0)

;Generates signed quotient only, no remainder

;Setup

;quotient is in B0 but the remainder is not

;correct)

;4 Quadrant Division of Integer, Signed Data (B1:B0 / X0)

;Generates signed quotient only, no remainder

;Setup

Software Techniques

8.4.3 Signed Dividend and Divisor with Remainder

The algorithms in the following code are another way to divide two signed numbers, where both the dividend or the divisor are signed two’s-complement numbers (positive or negative). These algorithms are the most general because they generate both a correct quotient and a correct remainder. The algorithms are referred to as 4 quadrant division because these algorithms allow any combination of positive or negative operands for the dividend and divisor. One algorithm is presented for division of fractional numbers and a second is presented for the division of integer numbers.

Division

;Four-Quadrant Division of Fractional, Signed Data (B1:B0 / X0)

;Generates signed quotient and remainder

;Setup

;quotient is in Y1 and the correct

;remainder in A1)

;Four-Quadrant Division of Integer, Signed Data (B1:B0 / X0)

;Generates signed quotient and remainder

;Setup

;(At this point, signed quotient in Y1, correct ; remainder in A1)