Software Techniques

8.1.1.4 JVS, JVC, BVS, and BVC Operations

Although there is no instruction for jumping or branching on overflow, such an operation can be emulated as shown in the following code. Note that the carry bit will be destroyed by this operation since it receives the result of the BFTSTH instruction. The following code shows JVS and BVC.

Example 8-4. JVS, JVC, BVS and BVC

;JVS Operation

;Emulated in 5 Icyc (4 Icyc if false), 4 Instruction Words

;BVC Operation

;Emulated in 5 Icyc (4 Icyc if false), 3 Instruction Words

8.1.1.5 Other Jumps and Branches on Condition Codes

Jumping and branching using some of the other condition codes (PL, MI, EC, ES, LC, LS) can be accomplished in the same manner as for overflow; see Section 8.1.1.4, “JVS, JVC, BVS, and BVC Operations.” Remember that this technique destroys the value in the carry bit. The following code shows JPL and BES.

Example 8-5. JPL and BES

;JPL Operation

;Emulated in 5 Icyc (4 Icyc if false), 4 Instruction Words

;BES Operation

;Emulated in 5 Icyc (4 Icyc if false), 3 Instruction Words

Similar code can be written for JMI, JEC, JES, JLMC, JLMS, BPL, BMI, BEC, BLMC, and BLMS. The JLMS and JLMC are used for “jump if limit set” and “jump if limit clear,” respectively; this is done to avoid any confusion with the JLS (“jump if lower or same”) instruction.

8.1.2 Negation Operations

The NEGW operation can be used to negate the upper two registers of the accumulator. The NEG operation can be used to negate the X0, Y0, or Y1 data ALU registers, negate an AGU register, or negate a memory location.

8.1.2.1 NEGW Operation

The NEGW operation can be emulated as shown in the following code:

;20-bit NEGW Operation

;Operates on EXT:MSP, Clears LSP, 3 Icyc

This correctly negates the upper 20 bits of the accumulator, but also destroys the A0 register.

Useful Instruction Operations

The NEG instruction can be used directly, executing in one instruction cycle, in cases where it is already known that the least significant portion (LSP) of an accumulator is $0000. This is true immediately after a value is moved to the A or B accumulator from memory or a register, as shown in the following code:

;Example of 1 Icyc NEGW Operation

;Works because A0 is already equal to $0000

The technique shown in the following code can be used for cases when 16-bit data is being processed and when it can be guaranteed that the LSP or extension register of the accumulator contains no required information:

;16-bit NEGW Operation

;Operates on MSP, Forces EXT to sign extension, LSP to $0, 2 Icyc

The following technique may be used for the case where the CC bit in the SR is set to a 1, the LSP may not be $0000, and the user is not interested in the values in the accumulator extension registers:

;16-bit NEGW Operation

;CC bit must be set, operates on MSP, doesn’t affect A0, 2 Icyc

;A2 may be incorrect

8.1.2.2Negating the X0, Y0, or Y1 Data ALU registers

Although the NEG instruction is supported on accumulators only, NEG can be emulated to perform a negation of the data ALU’s X0, Y0, or Y1 registers, as shown in the following code:

;NEG Operation

;Emulated at 2 Icyc

8.1.2.3 Negating an AGU register

It is possible to negate one of the AGU registers (Rn) without destroying any other register, as shown in the following code:

;NEG Operation

;Emulated at 3 Icyc

8.1.2.4 Negating a Memory Location

It is possible to negate a memory location, as shown in the following code:

;NEG Operation

;Emulated at 5 Icyc

When an accumulator is available, it may be faster to do this operation simply by moving the value to an accumulator, performing the operation there, and moving the result back to memory.