Interrupts and the Processing States

Figure 7-6. Repeated Illegal Instruction

In DO loops, if the illegal instruction is in the loop address (LA) location and the instruction preceding it (that is, at LA-1) is being interrupted, the loop counter (LC) will be decremented as if the loop had reached the LA instruction. When the interrupt service ends and the instruction flow returns to the loop, the instruction after the illegal instruction will be fetched (since it is the next sequential instruction in the flow).

7.3.8 Interrupt Latency

Interrupt latency represents the time between when an interrupt request first appears and when the first instruction in an interrupt service routine is actually executed. The interrupt can only take place on instruction boundaries, and so the length of execution of an instruction affects interrupt latency.

There are some special cases to consider. The SWI, STOP, and WAIT instructions are not interruptible. Likewise, the REP instruction and the instruction it repeats are not interruptible.

A REP instruction and the instruction that follows it are treated as a single two-word instruction, regardless of how many times it repeats the second instruction of the pair. Instruction fetches are suspended and will be reactivated only after the LC is decremented to one (see Figure 7-7). During the execution of n2 in Figure 7-7, no interrupts will be serviced. When LC finally decrements to one, the fetches are re-initiated, and pending interrupts can be serviced.