Exception Processing State

IRQA Mode IRQB Mode (Reserved)

Channel 6 IPL

Channel 5 IPL

Channel 4 IPL

Channel 3 IPL

Channel 2 IPL

Channel 1 IPL

Channel 0 IPL

* Indicates reserved bits, read as zero and should be written with zero for future compatibility

AA0057

Figure 7-2. Example Interrupt Priority Register

In the example interrupt priority register (IPR), shown in Figure 7-2, the interrupt for each on-chip peripheral device (channels 0–6) and for each external interrupt source (IRQA, IRQB), can be enabled or disabled under software control. The IPR also specifies the trigger mode of the external interrupt sources. Figure 7-3 shows how it might be programmed for different interrupts.

AA0058

Figure 7-3. Example On-Chip Peripheral and IRQ Interrupt Programming

7.3.5 Interrupt Sources

An interrupt request is a request to break out of currently executing code to enter an interrupt service routine. Interrupt requests in the DSP are generated from one of three sources: external hardware, internal hardware, and internal software. The internal hardware interrupt sources include all of the on-chip peripheral devices.

Each interrupt source has at least one associated interrupt vector, and some sources may have several interrupt vectors. The interrupt vector addresses for each interrupt source are listed in the interrupt vector table (Table 7-4). These addresses are usually located in either the first 64 or 128 locations of program memory. For further information on a device’s on-chip peripheral interrupt sources, see the device’s individual user’s manual.

Interrupts and the Processing States

When an interrupt request is recognized and accepted by the DSP core, a two-word JSR instruction is fetched from the interrupt vector table. Because the program flow is directed to a different starting address within the table for each different interrupt, the interrupt structure can be described as “vectored.” A vectored interrupt structure has low execution overhead. If it is known beforehand that certain interrupts will not be used or enabled, those locations within the table can instead be used for program or data storage.

7.3.5.1 External Hardware Interrupt Sources

The external hardware interrupt sources are listed below:

•RESET pin

•IRQA pin—priority level 0

•IRQB pin—priority level 0

An assertion of the RESET is not truly an interrupt, but rather it forces the chip into the reset processing state. Likewise, for any DSP chip that contains a COP timer, a time-out on this timer can also place the chip into the reset processing state. The reset processing state is at the highest priority and takes precedence over any interrupt, including an interrupt in progress.

Assertions on the IRQA and IRQB pins generate IRQA and IRQB interrupts, which are priority level 0 interrupts and are individually maskable. The IRQA and IRQB interrupt pins are internally synchronized with the processor’s internal clock and can be programmed as level-sensitive or edge-sensitive.

Edge-sensitive interrupts are latched as pending when a falling edge is detected on an IRQ pin. The IRQ pin’s interrupt-pending bit remains set until its associated interrupt is recognized and serviced by the DSP core. Edge-sensitive interrupts are automatically cleared when the interrupt is recognized and serviced by the DSP core. In an edge-sensitive interrupt the interrupt-pending bit is automatically cleared when the second vector location is fetched.

Level-sensitive interrupts, on the other hand, are never latched but go directly into the interrupt controller. A level-sensitive interrupt is examined and processed when the IRQ pin is low and the interrupt arbiter allows this interrupt to be recognized. Since there is no interrupt-pending bit associated with level-sensitive interrupts, the interrupt cannot not be cleared automatically when serviced; instead, it must be explicitly cleared by other means to prevent multiple interrupts.

NOTE:

On all level-sensitive interrupts, the interrupt must be externally released before interrupts are internally re-enabled. Otherwise, the processor will be interrupted repeatedly until the release of the level-sensitive interrupt.

When either the IRQA or IRQB pin is disabled in the IPR, any interrupt request on its associated pin is ignored, regardless of whether the input was defined as level-sensitive or edge-sensitive. If the interrupt input is defined as edge-sensitive, its interrupt-pending bit will remain in the reset state for as long as the interrupt pin is disabled. If the interrupt is defined as level-sensitive, its edge-detection latch will stay in the reset state. If the level-sensitive interrupt is disabled while it is pending, it will be cancelled. However, if the interrupt has been fetched, it normally will not be cancelled.

The level-sensitive interrupt capability is useful for the case where there is more than one external interrupt source, yet only one IRQ pin is available. In this case the interrupts are wire ORed onto a single IRQ pin with a resistor pull-up, and any one of these can assert an interrupt. It is important that the interrupt service routine poll each device, and, after finding the source of the interrupt, it must clear the conditions causing the interrupt request.

Exception Processing State

7.3.5.2 DSP Core Hardware Interrupt Sources

Other interrupt sources include the following:

•Stack error interrupt—priority level 1

•OnCE trap—priority level 1

•All on-chip peripherals (such as timers and serial ports)—priority level 0

An overflow of the hardware stack (HWS) causes a stack overflow interrupt that is vectored to P:$000A (see Section 5.1.7, “Hardware Stack,” on page 5-6). Encountering the stack overflow condition means that too many DO loop addresses have been stacked and that the oldest top-of-loop address has been lost. The stack error is non-recoverable. The stack error condition refers to hardware stack overflow and does not affect the software stack pointed to by the stack pointer (SP) register in any manner.

The OnCE trap interrupt is an interrupt that can be setup in the OnCE debug port accessible through the JTAG pins. This gives the debug port the capability to generate an interrupt on a trigger condition such as the matching of an address in the OnCE port (see Section 9.3, “OnCE Port,” on page 9-4 for more information).

In addition to these sources there are seven general-purpose interrupt channels, Ch0 through Ch6, available for use by on-chip peripherals such as timers and serial ports. Each channel can independently generate an interrupt request, each can be individually masked, and each channel can have one or more dedicated locations in the interrupt vector table. Typically, one channel is assigned to each on-chip peripheral, but, in cases where there are more than seven peripherals that can generate interrupts, it is possible to put more than one peripheral on a single interrupt channel.

7.3.5.3 DSP Core Software Interrupt Sources

The two software interrupt sources are listed below:

•Software interrupt (SWI)—priority level 1

•Illegal instruction interrupt (Ill)— priority level 1

A SWI is a non-maskable interrupt that is serviced immediately following the SWI instruction execution (that is, no other instructions are executed between the SWI instruction and the JSR instruction found in the interrupt vector table). The difference between an SWI and a JSR instruction is that the SWI sets the interrupt mask to prevent level 0–maskable interrupts from being serviced. The SWI’s ability to mask out lower-level interrupts makes it very useful for setting breakpoints in monitor programs or for making a system call in a simple operating system. The JSR instruction does not affect the interrupt mask.

The illegal instruction interrupt is also a non-maskable interrupt (priority level 1). It is serviced immediately following the execution or attempted execution of an illegal instruction (an undefined operation code). Illegal exceptions are fatal errors. The JSR located in the illegal instruction interrupt vector will stack the address of the instruction immediately after the illegal instruction.