Exception Processing State

Example 7-2. Common Pipeline Dependency Code Sequence

In this case, before the first MOVE instruction has written R2 during its execution cycle, the second MOVE has accessed the old R2, using the old contents of R2. This is because the address for indirect moves is formed during the decode cycle. This overlapping instruction execution in the pipeline causes the pipeline effect.

After an address register has been written by a MOVE instruction, one instruction cycle should be allowed before the new contents are available for use as an address register by another MOVE instruction. The proper instruction sequence follows:

Section 4.4, “Pipeline Dependencies,” on page 4-33 contains more details on interlocks caused during address generation.

7.3 Exception Processing State

The exception processing state is the state where the DSP core recognizes and processes interrupts that can be generated by conditions inside the DSP or from external sources. Upon the occurrence of an event, interrupt processing transfers control from the currently executing program to an interrupt service routine, with the ability to later return to the current program upon completion of the interrupt service routine. In digital signal processing, some of the main uses of interrupts are to transfer data between DSP memory and a peripheral device or to begin execution of a DSP algorithm upon reception of a new sample. An interrupt can also be used to exit the DSP’s low-power wait processing state.

An interrupt will cause the processor to enter the exception processing state. Upon entering this state, the current instruction in decode executes normally. The next fetch address is supplied by the interrupt controller and points into the interrupt vector table (Table 7-4 on page 7-7). During this fetch the PC is not updated. The instruction located at these two addresses in the interrupt vector table must always be a two-word, unconditional jump-to-subroutine instruction (JSR). Note that the interrupt controller only fetches the second word of the JSR instruction. This results in the program changing flow to an interrupt routine, and a context switch is performed.

There are many sources for interrupts on the DSP56800 Family of chips, and some of these sources can generate more than one interrupt. Interrupt requests can be generated from conditions within the DSP core, from the DSP peripherals, or from external pins. The DSP core features a prioritized interrupt vector scheme with up to 64 vectors to provide faster interrupt servicing. The interrupt priority structure is discussed in Section 7.3.3, “Interrupt Priority Structure.”

7.3.1 Sequence of Events in the Exception Processing State

The following steps occur in exception processing:

1.A request for an interrupt is generated either on a pin, from the DSP core, from a peripheral on the DSP chip, or from an instruction executed by the DSP core. Any hardware interrupt request from a pin is first synchronized with the DSP clock.

Interrupts and the Processing States

2.The request for an interrupt by a particular source is latched in an interrupt-pending flag if it is an edge or non-maskable interrupt (all other interrupts are not latched and must remain asserted in order to be serviced). For peripherals that can generate more than one interrupt request and have more than one interrupt vector, the interrupt arbiter only sees one request from the peripheral active at a time.

3.All pending interrupt requests are arbitrated to select which interrupt will be processed. The arbiter automatically ignores any interrupts with an interrupt priority level (IPL) lower than the interrupt mask level specified in the SR. If there are any remaining requests, the arbiter selects the remaining interrupt with the highest IPL, and the chip enters the exception processing state (see Figure 7-1).

4.The interrupt controller then freezes the program counter (PC) and fetches the JSR instruction located at the two interrupt vector addresses associated with the selected interrupt. It is required that the instruction located at the interrupt vector address must be a two-word JSR instruction. Note that only the second word of the JSR instruction is fetched; the first word of the JSR is provided by the interrupt controller.

5.The interrupt controller places this JSR instruction into the instruction stream and then releases the PC, which is used for the next instruction fetch. Arbitration among the remaining interrupt requests is allowed to resume. The next interrupt arbitration then begins.

6.The execution of the JSR instruction stacks the PC and the SR as it transfers control to the first instruction in the interrupt service routine. These two stacked registers contain the 16-bit return address that will later be used to return to the interrupted code, as well as the condition code state. In addition, the IPL is raised to level 1 to disallow any level 0 interrupts. Note that the OnCE trap, stack error, illegal instruction, and SWI can still generate interrupts because these are level 1 interrupts and are non-maskable.

The exception processing state is completed when the processor executes the JSR instruction located in the interrupt vector table and the chip enters the normal processing state. As it enters the normal processing state, it begins executing the first instruction in the interrupt service routine. Each interrupt service routine should return to the main program by executing an RTI instruction.

Interrupt routines for level 0 interrupts are interruptible by higher priority interrupts. Figure 7-1 shows an example of processing an interrupt.

AA0056

Figure 7-1. Interrupt Processing

Exception Processing State

Steps 1 through 3 listed on page page 7-5 require two additional instruction cycles, effectively making the interrupt pipeline five levels deep.

7.3.2 Reset and Interrupt Vector Table

The interrupt vector table specifies the addresses that the processor accesses once it recognizes an interrupt and begins exception processing. Since peripherals can also generate interrupts, the interrupt vector map for a given chip is specified by all sources on the DSP core as well as all peripherals that can generate an interrupt. Table 7-4 lists the reset and interrupt vectors available on DSP56800-based DSP chips. The interrupt vectors used by on-chip peripherals, or by additional device-specific interrupt will be listed in the user’s manual for that chip.

Interrupts and the Processing States

It is required that a two-word JSR instruction is present in any interrupt vector location that may be fetched during exception processing. If an interrupt vector location is unused, then the JSR instruction is not required.

The hardware reset and COP reset are special cases because they are reset vectors, not interrupt vectors. There is no IPL specified for these two because these conditions reset the chip and reset takes precedence over any interrupt. Typically a two-word JMP instruction is used in the reset vectors. The hardware reset vector will either be at address $0000 or $E000 and the COP reset vector will either be at $0002 or $E002 depending on the operating mode of the chip. The different operating modes are discussed in

Section 5.1.9.1, “Operating Mode Bits (MB and MA)—Bits 1–0,” on page 5-10.

7.3.3 Interrupt Priority Structure

Interrupts are organized in a simple priority structure. Each interrupt source has an associated IPL: Level 0 or Level 1. Level 0, the lowest level, is maskable, and Level 1 is non-maskable. Table 7-5 summarizes the priority levels and their associated interrupt sources.

Table 7-5. Interrupt Priority Level Summary

The interrupt mask bits (I1, I0) in the SR reflect the current priority level and indicate the IPL needed for an interrupt source to interrupt the processor (see Table 7-6). Interrupts are inhibited for all priority levels below the current processor priority level. Level 1 interrupts, however, are not maskable and, therefore, can always interrupt the processor.

Table 7-6. Interrupt Mask Bit Definition in the Status Register

7.3.4 Configuring Interrupt Sources

The interrupt unit in the DSP56800 core supports seven interrupt channels for use by on-chip peripherals, in addition to the IRQ interrupts and interrupts generated by the DSP core. Each maskable interrupt source can individually be enabled or disabled as required by the application. The exact method for doing so is dependant on the particular DSP56800-based device, as some of the interrupt handling logic is implemented as an on-chip peripheral.

One example of how interrupts can be enabled and disabled, and their priority level established, is with an interrupt priority register (IPR).