Interrupts and the Processing States

5.Clears the status register’s (SR) loop flag and condition code bits and sets the interrupt mask bits

6.Clears the following bits in the operating mode register: nested looping, condition codes, stop delay, rounding, and external X memory

The DSP remains in the reset state until the RESET pin is deasserted. When hardware deasserts the RESET pin, the following occur:

1.The chip operating mode bits in the OMR are loaded from an external source, typically mode select pins; see the appropriate device manual for details.

2.A delay of 16 instruction cycles (NOPs) occurs to sync the local clock generator and state machine.

3.The chip begins program execution at the program memory address defined by the state of the MA and MB bits in the OMR and the type of reset (hardware or COP time-out). The first instruction must be fetched and then decoded before execution. Therefore, the first instruction execution is two instruction cycles after the first instruction fetch.

After this last step, the DSP enters the normal processing state upon exiting reset. It is also possible for the DSP to enter the debug processing state upon exiting reset when system debug is underway.

7.2 Normal Processing State

The normal processing state is the typical state of the processor where it executes instructions in a three-stage pipeline. This includes the execution of simple instructions such as moves or ALU operations as well as jumps, hardware looping, bit-field instructions, instructions with parallel moves, and so on. Details about the execution of the individual instructions can be found in Appendix A, “Instruction Set Details.” The chip must be reset before it can enter the normal processing state.

7.2.1 Instruction Pipeline Description

The instruction-execution pipeline is a three-stage pipeline, which allows most instructions to execute at a rate of one instruction per instruction cycle. For the case where there are no off-chip memory accesses, or for the case of a single off-chip access with no wait states, one instruction cycle is equivalent to two machine cycles. A machine cycle is defined as one cycle of the clock provided to the DSP core. Certain instructions, however, require more than one instruction cycle to execute. These instructions include the following:

•Instructions longer than one word

•Instructions using an addressing mode that requires more than one cycle

•Instructions that cause a control-flow change

Pipelining allows instruction executions to overlap so that the fetch-decode-execute operations of a given instruction occur concurrently with the fetch-decode-execute operations of other instructions. Specifically, while the processor is executing one instruction, it is decoding the next instruction and fetching a third instruction from program memory. The processor fetches only one instruction word per instruction cycle; if an instruction is two words in length, it fetches the additional word with an additional cycle before it fetches the next instruction.

Normal Processing State

Table 7-2. Instruction Pipelining

Table 7-2 demonstrates pipelining. “F1,” “D1,” and “E1” refer to the fetch, decode, and execute operations of the first instruction, respectively. The third instruction, which contains an instruction extension word, takes two instruction cycles to execute. Although it takes three instruction cycles (six machine cycles) for the pipeline to fill and the first instruction to execute, an instruction usually executes on each instruction cycle thereafter (two machine cycles).

7.2.2 Instruction Pipeline with Off-Chip Memory Accesses

The three sets of internal on-chip address and data buses (XAB1/CGDB, XAB2/XDB2, PAB/PDB) allow for fast memory access when memories are being accessed on-chip. The DSP can perform memory accesses on all three bus pairs in a single instruction cycle, permitting the fetch of an instruction concurrently with up to two accesses to the X data memory. Thus, for applications where all program and data is located in on-chip memory, there is no speed penalty when performing up to three memory accesses in a single instruction.

Similarly, the external address and data bus also allows for fast program execution. For the case where only program memory is external to the chip or only X data memory is external (XAB1/CDGB bus pair), the DSP chip will still execute programs at full speed if there are no wait states programmed on the external bus by the user. For the case where an instruction requires an external program fetch and an external X data memory access simultaneously, the instruction will still operate correctly. The instruction is automatically stretched an additional instruction cycle so that the two external accesses may be performed correctly, and wait states are inserted accordingly. All this occurs transparently to the user to allow for easier program development.

This information is summarized in Table 7-3, which shows how the chip automatically inserts instruction cycles and wait states for an instruction that is simultaneously accessing program and data memory. For dual parallel read instructions, the second X memory access that uses XAB2/XDB2 must always be done to on-chip memory. This second access may never access external off-chip memory.

Interrupts and the Processing States

Table 7-3. Additional Cycles for Off-Chip Memory Accesses

Note: The ‘mv’ and ‘mvm’ cycle time values reflect the additional time required for all MOVE instructions and for MOVEM instructions, respectively.

7.2.3 Instruction Pipeline Dependencies and Interlocks

The pipeline is normally transparent to the user. However, there are certain instruction-sequence combinations where the pipeline will affect the program execution. Such situations are best described by case studies. Most of these restricted sequences occur because either all addresses are formed during instruction decode or they are the result of contention for an internal resource such as the SR.

If the execution of an instruction depends on the relative location of the instruction in a sequence of instructions, there is a pipeline effect.

It is possible to see if there is a pipeline dependency. To test for a suspected pipeline effect, compare the execution of the suspect instruction when it directly follows the previous instruction and when four NOPs are inserted between the two. If there is a difference, it is caused by a pipeline effect. The assembler flags instruction sequences with potential pipeline effects so that the user can determine if the operation will execute as expected.

Example 7-1. Pipeline Dependencies in Similar Code Sequences

No Pipeline Effect

ORC #$0001,SR ; Changes carry bit at the end of execution time slot JCS LABEL ; Reads condition codes in SR in its

; execution time slot

The JCS instruction will test the carry bit modified by the ORC without any pipeline effect in this code segment.

Pipeline Effect

ORC #$0008,OMR ; Sets EX bit at execution time slot

MOVE X:$17,A ; Reads internal memory instead of external ; memory

A pipeline effect occurs because the address of the MOVE is formed at its decode time before the ORC changes the EX bit (which changes the memory map) in the ORC’s execution time slot. The following code produces the expected results of reading the external ROM:

ORC #$0008,OMR ; Sets EX bit at execution time slot

NOP ; Delays the MOVE so it will read the updated memory map MOVE X:$17,A ; Reads external memory