Chapter 2

Core Architecture Overview

The DSP56800 core architecture is a 16-bit multiple-bus processor designed for efficient real-time digital signal processing and general purpose computing. The architecture is designed as a standard programmable core from which various DSP integrated circuit family members can be designed with different on-chip and off-chip memory sizes and on-chip peripheral requirements. This chapter presents the overall core architecture and the general programming model. More detailed information on the data ALU, AGU, program controller, and JTAG/OnCE blocks within the architecture are found in later chapters.

2.1 Core Block Diagram

The DSP56800 core is composed of functional units that operate in parallel to increase the throughput of the machine. The program controller, AGU, and data ALU each contain their own register set and control logic, so each may operate independently and in parallel with the other two. Likewise, each functional unit interfaces with other units, with memory, and with memory-mapped peripherals over the core’s internal address and data buses. The architecture is pipelined to take advantage of the parallel units and significantly decrease the execution time of each instruction.

For example, it is possible for the data ALU to perform a multiplication in a first instruction, for the AGU to generate up to two addresses for a second instruction, and for the program controller to be fetching a third instruction. In a similar manner, it is possible for the bit-manipulation unit to perform an operation of the third instruction described above in place of the multiplication in the data ALU.

The major components of the core are the following:

•Data ALU

•AGU

•Program controller and hardware looping unit

•Bus and bit-manipulation unit

•OnCE debug port

•Address buses

•Data buses

Figure 2-1 on page 2-2 shows a block diagram of the CPU architecture.

Core Architecture Overview

Bus and Bit

Manipulation

Unit

Y1 Y0 X0 A2 A1 A0 B2 B1 B0

OnCE

MAC

and

ALU

Figure 2-1. DSP56800 Core Block Diagram

Note that Figure 2-1 illustrates two methods for connecting peripherals to the DSP56800 core: using the Motorola-standard IP-BUS interface or via a dedicated peripheral global data bus (PGDB). When the IP-BUS interface is used, peripheral registers may be memory mapped into any data (X) memory address range and are accessed with standard X-memory reads and writes. When the PGDB interface is used, peripheral registers are mapped to the last 64 locations in X memory and are accessed with a special memory addressing mode (see Section 4.2.4.3, “I/O Short Address (Direct Addressing): <pp>,” on

page 4-23).

The interface method used to connect to peripherals is dependent on the specific DSP56800-based device being used. Consult your device user’s manual for more information on peripheral interfacing.

Core Block Diagram

2.1.1 Data Arithmetic Logic Unit (ALU)

The data arithmetic logic unit (ALU) performs all of the arithmetic and logical operations on data operands. It consists of the following:

•Three 16-bit input registers (X0, Y0, and Y1)

•Two 32-bit accumulator registers (A and B)

•Two 4-bit accumulator extension registers (A2 and B2)

•An accumulator shifter (AS)

•One data limiter

•One 16-bit barrel shifter

•One parallel (single cycle, non-pipelined) multiply-accumulator (MAC) unit

The data ALU is capable of multiplication, multiply-accumulation (with positive or negative accumulation), addition, subtraction, shifting, and logical operations in one instruction cycle. Arithmetic operations are done using two’s-complement fractional or integer arithmetic. Support is also provided for unsigned and multi-precision arithmetic.

Data ALU source operands may be 16, 32, or 36 bits and may individually originate from input registers, memory locations, immediate data, or accumulators. ALU results are stored in one of the accumulators. In addition, some arithmetic instructions store their 16-bit results either in one of the three data ALU input registers or directly in memory. Arithmetic operations and shifts can have a 16-bit or a 36-bit result. Logical operations are performed on 16-bit operands and always yield 16-bit results.

Data ALU register values can be transferred (read or write) across the core global data bus (CGDB) as 16-bit operands. The X0 register value can also be written by X memory data bus two (XDB2) as a 16-bit operand. Refer to Chapter 3, “Data Arithmetic Logic Unit,” for a detailed description of the data ALU.

2.1.2 Address Generation Unit (AGU)

The address generation unit (AGU) performs all of the effective address calculations and address storage necessary to address data operands in memory. The AGU operates in parallel with other chip resources to minimize address-generation overhead. It contains two ALUs, allowing the generation of up to two 16-bit addresses every instruction cycle: one for either X memory address bus one (XAB1) or program address bus (PAB) and one for X memory address bus two (XAB2). The ALU can directly address 65,536 locations on the XAB1 or XAB2 and 65,536 locations on the PAB, totaling 131,072 sixteen-bit data words. It supports a complete set of addressing modes. Its arithmetic unit can perform both linear and modulo arithmetic.

The AGU contains the following registers:

•Four address registers (R0-R3)

•A stack pointer register (SP)

•An offset register (N)

•A modifier register (M01)

•A modulo arithmetic unit

•An incrementer/decrementer unit

Core Architecture Overview

The address registers are 16-bit registers that may contain an address or data. Each address register can provide an address for the XAB1 and PAB address buses. For instructions that read two values from X data memory, R3 provides an address for the XAB2, and R0 or R1 provides an address for the XAB1. The modifier and offset registers are 16-bit registers that control updating of the address registers. The offset register can also be used to store 16-bit data. AGU registers may be read or written by the CGDB as 16-bit operands. Refer to Chapter 4, “Address Generation Unit,” for a detailed description of the AGU.

2.1.3 Program Controller and Hardware Looping Unit

The program controller performs the following:

•Instruction prefetch

•Instruction decoding

•Hardware loop control

•Interrupt (exception) processing

Instruction execution is carried out in other core units such as the data ALU, AGU, or bit-manipulation unit. The program controller consists of the following:

•A program counter unit

•Instruction latch and decoder

•Hardware looping control logic

•Interrupt control logic

•Status and control registers

Located within the program controller are the following:

•Four user-accessible registers:

—Loop address register (LA)

—Loop count register (LC)

—Status register (SR)

—Operating mode register (OMR)

•A program counter (PC)

•A hardware stack (HWS)

In addition to the tasks listed above, the program controller also controls the memory map and operating mode. The operating mode and memory map are programmable via the OMR, and are established after reset by external interface pins.

The HWS is a separate internal last-in-first-out (LIFO) buffer of two 16-bit words that stores the address of the first instruction in a hardware DO loop. When a new hardware loop is begun by executing the DO instruction, the address of the first instruction in the loop is stored (pushed) on the “top” location of the HWS, and the LF bit in the SR is set. The previous value of the loop flag (LF) bit is copied to the OMR’s NL bit. When an ENDDO instruction is encountered or a hardware loop terminates naturally, the 16-bit address in the “top” location of the HWS is discarded, and the LF bit is updated with the value in the OMR’s nested looping (NL) bit.

The program controller is described in detail in Chapter 5, “Program Controller.” For more details on program looping, refer to Section 5.3, “Program Looping,” on page 5-14 and Section 8.6, “Loops,” on page 8-20. For information on reset and interrupts, refer to Chapter 7, “Interrupts and the Processing States.”