Instruction Set Introduction

Table 6-8. Program Control Instruction List (Continued)

6.5 Instruction Aliases

The DSP56800 assembler provides a number of additional useful instruction mnemonics that are actually aliases to other instructions. Each of these instructions is mapped to one of the core instructions and disassembles as such.

6.5.1 ANDC, EORC, ORC, and NOTC Aliases

The DSP56800 instruction set does not support logical operations using 16-bit immediate data. It is possible to achieve the same result, however, using the bit-manipulation instructions. To simplify implementing these operations, the DSP56800 assembler provides the following operations:

•ANDC—logically AND a 16-bit immediate value with a destination

•EORC—logically exclusive OR a 16-bit immediate value with a destination

•ORC—logically OR a 16-bit immediate value with a destination

•NOTC—logical one’s-complement of a 16-bit destination

These operations are not new instructions, but aliases to existing bit-manipulation instructions. They are mapped as shown in Table 6-9.

Table 6-9. Aliases for Logical Instructions with Immediate Data

Instruction Aliases

Note that for the ANDC instruction, a one’s-complement of the mask value is used when remapping to the BFCLR instruction. For the NOTC instruction, all bits in the 16-bit mask are set to one.

In Example 6-2, an immediate value is logically ORed with a location in memory.

Example 6-2. Logical OR with a Data Memory Location

The assembler translates this instruction into BFSET #$00FF,X:$400, which performs the same operation. If the assembled code is later disassembled, it will appear as a BFSET instruction.

6.5.2 LSLL Alias

Because the LSLL instruction operates identically to an arithmetic left shift, this instruction is actually assembled as an ASLL instruction. When the assembler encounters the LSLL mnemonic, an ASLL instruction is assembled. See Table 6-10.

Table 6-10. LSLL Instruction Alias

6.5.3 ASL Alias

Because the ASL instruction operates similarly to a logical left shift when executed on the Y1, Y0, and X0 registers, this instruction is actually assembled as an LSL instruction. Note that while the result in the destination register will be the same as if an arithmetic shift had been performed, condition codes are calculated based on a logic shift and might differ from the expected result. See Table 6-11.

The ASL instruction is not aliased to LSL when the register specified is one of the accumulator registers.

Table 6-11. ASL Instruction Remapping

6.5.4 CLR Alias

Because CLR operates identically to a MOVE instruction with an immediate value of zero, a MOVE instruction is used to implement CLR when the specified register is a 16-bit register. When the assembler encounters the CLR mnemonic in a program, it assembles a MOVE #0,<register> instruction in its place. See Table 6-12.

NOTE:

This operation does not apply to the CLR instruction when it is performed on the A or B accumulators.