Instruction Set Introduction

6.4 Instruction Groups

The instruction set is divided into the following groups:

•Arithmetic

•Logical

•Bit manipulation

•Looping

•Move

•Program control

Each instruction group is described in the following subsections. In addition, Section 6.5.2, “LSLL Alias,” includes a useful summary for every instruction and the addressing modes and operand registers allowed for each instruction. Detailed information on each instruction is given in Appendix A, “Instruction Set Details.”

6.4.1 Arithmetic Instructions

The arithmetic instructions perform all of the arithmetic operations within the data ALU. They may affect a subset or all of the condition code register bits. Arithmetic instructions are typically register based (register-direct addressing modes are used for operands) so that the data ALU operation indicated by the instruction does not use the CGDB or the XDB2, although some instructions can also operate on immediate data or operands in memory.

Optional data transfers (parallel moves) may be specified with many arithmetic instructions. This allows for parallel data movement over the CGDB and over the XDB2 during a data ALU operation. This allows new data to be pre-fetched for use in following instructions and results calculated by previous instructions to be stored. Arithmetic instructions typically execute in one instruction cycle, although some of the operations may take additional cycles with different operand addressing modes. The arithmetic instructions are the only class of instructions that allow parallel moves.

In addition to the arithmetic shifts presented here, other types of shifts are also available in the logical instruction group. See Section 6.4.2, “Logical Instructions.” Table 6-3 lists the arithmetic instructions.

Instruction Groups

Table 6-3. Arithmetic Instructions List (Continued)

1.These instructions do not allow parallel data moves.

6.4.2Logical Instructions

The logical instructions perform all of the logical operations within the data ALU. They also affect the condition code register bits. Logical instructions are register based. So are the arithmetic instructions in Table 6-3, and, again, some can also operate on operands in memory. Optional data transfers are not permitted with logical instructions. These instructions execute in one instruction cycle.

Table 6-4 lists the logical instructions.

Instruction Set Introduction

6.4.3 Bit-Manipulation Instructions

The bit-manipulation instructions perform one of three tasks:

•Testing a field of bits within a word

•Testing and modifying a field of bits in a word

•Conditionally branching based on a test of bits within the upper or lower byte of a word

Bit-field instructions can operate on any X memory location, peripheral, or DSP core register. BFTSTH and BFTSTL can test any field of the bits within a 16-bit word. BFSET, BFCLR, and BFCHG can test any field of the bits within a 16-bit word and then set, clear, or invert bits in this word, respectively. BRSET and BRCLR can only test an 8-bit field in the upper or lower byte of the word, and then conditionally branch based on the result of the test. The carry bit of the condition code register contains the result of the bit test for each instruction. These instructions are operations of the read-modify-write type. The BFTSTH, BFTSTL, BFSET, BFCLR, and BFCHG instructions execute in two or three instruction cycles. The BRCLR and BRSET instructions execute in four to six instruction cycles.

Table 6-5 lists the bit-manipulation instructions.

Instruction Groups

Table 6-5. Bit-Field Instruction List (Continued)

NOTE:

Due to instruction pipelining, if an AGU register (Rn, N, SP, or M01) is directly changed with a bit-field instruction, the new contents may not be available for use until the second following instruction (see the restrictions discussed in Section 4.4, “Pipeline Dependencies,” on page 4-33).

See Section 8.1.1, “Jumps and Branches,” on page 8-2 for other instructions that can be synthesized.

6.4.4 Looping Instructions

The looping instructions establish looping parameters and initiate zero-overhead program looping. They allow looping on a single instruction (REP) or a block of instructions (DO). For DO looping, the address of the first instruction in the program loop is saved on the hardware stack to allow no-overhead looping. The last address of the DO loop is specified as a 16-bit absolute address. No locations in the hardware stack are required for the REP instruction. The ENDDO instruction is used only when breaking out of the loop; otherwise, it is better to use MOVE #1,LC. This is discussed in more detail in Section 8.6.6, “Early Termination of a DO Loop,” on page 8-25.

Table 6-6 lists the loop instructions.

6.4.5 Move Instructions

The move instructions move data over the various data buses: CGDB, PGDB, XDB2, and PDB. Move instructions do not affect the condition code register, except for the limit bit if limiting is performed when reading a data ALU accumulator register. These instructions do not allow optional data transfers. In addition to the following move instructions, there are parallel moves that can be used simultaneously with many of the arithmetic instructions. The parallel moves are shown in Table 6-34 on page 6-29 and

Instruction Set Introduction

Table 6-35 on page 6-30 and are discussed in detail in Section 6.1, “Introduction to Moves and Parallel Moves,” and Appendix A, “Instruction Set Details.” The LEA instruction is also included in this instruction group.