Instruction Formats

Figure 6-2 illustrates a double parallel move, which uses one program word and executes in one instruction cycle.

Figure 6-2. Dual Parallel Move

In the dual parallel move, the following occurs.

1.The contents of the X0 and Y0 registers are multiplied, this result is added to the A accumulator, and the final result is stored in the A accumulator.

2.The contents of the X data memory location pointed to with the R0 register are moved into the Y0 register.

3.The contents of the X data memory location pointed to with the R3 register are moved into the X0 register.

4.After completing the memory moves, the R0 register is post-updated with the contents of the N register, and the R3 register is decremented by one.

Both types of parallel moves use a subset of available DSP56800 addressing modes, and the registers available for the move portion of the instruction are also a subset of the total set of DSP core registers. These subsets include the registers and addressing modes most frequently found in high-performance numeric computation and DSP algorithms. Also, the parallel moves allow a move to occur only with an arithmetic operation in the data ALU. A parallel move is not permitted, for example, with a JMP, LEA, or BFSET instruction.

6.2 Instruction Formats

Instructions are one, two, or three words in length. The instruction is specified by the first word of the instruction. The additional words may contain information about the instruction itself or may contain an operand for the instruction. Samples of assembly language source code for several instructions are shown in Table 6-2.

From the instruction formats listed in Table 6-2, it can be seen that the DSP offers parallel processing using the data ALU, AGU, program controller, and bit-manipulation unit. In the parallel move example, the DSP can perform a designated ALU operation (data ALU) and up to two data transfers specified with address register updates (AGU), and will also decode the next instruction and fetch an instruction from program memory (program controller), all in one instruction cycle. When an instruction is more than one word in length, an additional instruction-execution cycle is required. Most instructions involving the data ALU are register based (that is, operands are in data ALU registers) and allow the programmer to keep each parallel processing unit busy. Instructions that are memory oriented (for example, a bit-manipulation instruction), all logical instructions, or instructions that cause a control flow change (such as a jump) prevent the use of all parallel processing resources during their execution.

Instruction Set Introduction

Table 6-2. Instruction Formats

1.Indicates data ALU, AGU, program controller, or bit-manipulation operation to be performed.

2.Specifies the operands used by the opcode.

3.Specifies optional data transfers over the CGDB bus.

4.Specifies optional data transfers over the XDB2 bus.

5.Specifies optional data transfers over the PDB bus.

Programming Model

6.3 Programming Model

The registers in the DSP56800 core programming model are shown in Figure 6-3.

Data Arithmetic Logic Unit

Address Generation Unit

Program Controller Unit

AA0007

Figure 6-3. DSP56800 Core Programming Model