Chapter 5

Program Controller

The program controller unit is one of the three execution units in the central processing module. The program controller performs the following:

•Instruction fetching

•Instruction decoding

•Hardware DO and REP loop control

•Exception (interrupt) processing

This section covers the following:

•The architecture and programming model of the program controller

•The operation of the software stack

•A discussion of program looping

Details of the instruction pipeline and the different processing states of the DSP chip, including reset and interrupt processing, are covered in Chapter 7, “Interrupts and the Processing States.”

5.1 Architecture and Programming Model

A block diagram of the program controller is shown in Figure 5-1 on page 5-2, and its corresponding programming model is shown in Figure 5-2 on page 5-3. The programmer views the program controller as consisting of five registers and a hardware stack (HWS). In addition to the standard program flow-control resources such as a program counter (PC) and status register (SR), the program controller features registers dedicated to supporting the hardware DO loop instruction—loop address (LA), loop counter (LC), and the hardware stack—and an operating mode register (OMR) defining the DSP operating modes.

The blocks and registers within the program controller are explained in the following subsections.

IPR

Interrupt Control

Interrupt Request

External Mode

Select Pin(s)

OMR

Control Bits to DSP Core

Condition Codes from Data ALU

SR

Figure 5-1. Program Controller Block Diagram

Architecture and Programming Model

Program Controller

AA0009

Figure 5-2. Program Controller Programming Model

5.1.1 Program Counter

The program counter (PC) is a 16-bit register that contains the address of the next location to be fetched from program memory space. The PC may point to instructions, data operands, or addresses of operands. Reference to this register is always implicit and is implied by most instructions. This special-purpose address register is stacked when hardware DO looping is initiated (on the hardware stack), when a jump to a subroutine is performed (on the software stack), and when interrupts occur (on the software stack).

5.1.2 Instruction Latch and Instruction Decoder

The instruction latch is a 16-bit internal register used to hold all instruction opcodes fetched from memory. The instruction decoder, in turn, uses the contents of the instruction latch to generate all control signals necessary for pipeline control—for normal instruction fetches, jumps, branches, and hardware looping.

5.1.3 Interrupt Control Unit

The interrupt control unit receives all interrupt requests, arbitrates among them, and then checks the highest-priority interrupt request against the interrupt mask bits for the DSP core (I1 and I0 in the SR). If the requesting interrupt has higher priority than the current priority level of the DSP core, then exception processing begins. When exception processing begins, the interrupt control unit provides the address of the interrupt vector for interrupts generated on the DSP core, whereas the peripherals generate the vector address for interrupts generated by an on-chip peripheral.

Interrupts have a simple priority structure with levels zero or one. Level 0 is the lowest interrupt priority level (IPL) and is maskable. Level 1 is the highest level and is not maskable. Two interrupt mask bits in the SR reflect the current IPL of the DSP core and indicate the level needed for an interrupt source to interrupt the processor.

The DSP56800 core provides support for internal (on-chip) peripheral interrupts and two external interrupt sources, IRQA and IRQB. The interrupt control unit arbitrates between interrupt requests generated externally and by the on-chip peripherals.

Asserting the reset pin causes the DSP core to enter the reset processing state. This has higher priority and overrides any activity in the interrupt control unit and the exception processing state.

Program Controller

Details of interrupt arbitration and the exception processing state are discussed in Section 7.3, “Exception Processing State,” on page 7-5. The reset processing state is discussed in Section 7.1, “Reset Processing State,” on page 7-1.

5.1.4 Looping Control Unit

The looping control unit provides hardware dedicated to support loops, which are frequent constructs in DSP algorithms.

The repeat instruction (REP) loads the 13-bit LC register with a value representing the number of times the next instruction is to be repeated. The instruction to be repeated is only fetched once per loop, so power consumption is reduced, and throughput is increased when running from external program memory by decreasing the number of external fetches required.

The DO instruction loads the 13-bit LC register with a value representing the number of times the loop should be executed, loads the LA register with the address of the last instruction word in the loop (fetched only once per loop), and sets the loop flag (LF) bit in the SR. The top-of-loop address is stacked on the HWS so the loop can be repeated with no overhead. When the LF in the SR is asserted, the loop state machine will compare the PC contents to the contents of the LA to determine if the last instruction word in the loop was fetched. If the last word was fetched, the LC contents are tested for one. If LC is not equal to one, then it is decremented, and the contents of the HWS (the address of the first instruction in the loop) are read into the PC, effectively executing an automatic branch to the top of the loop. If the LC is equal to one, then the LF in the SR is restored with the contents of the OMR’s nested looping (NL) bit, the top-of-loop address is removed from the HWS, and instruction fetches continue at the incremented PC value (LA + 1).

Nested loops are supported by stacking the address of the first instruction in the loop (top of loop) in the HWS and copying the LF bit into the OMR’s NL bit prior to the execution of the first instruction in the loop. The user, however, must explicitly stack the LA and LC registers as described in Section 8.6.4, “Nested Loops,” on page 8-22.

Looping is described in more detail in Section 5.3, “Program Looping,” and Section 8.6, “Loops,” on page 8-20.

5.1.5 Loop Counter

The loop counter (LC) is a special 13-bit down counter used to specify the number of times to repeat a hardware program loop (DO and REP loops). When the end of a hardware program loop is reached, the contents of the loop counter register are tested for one. If the loop counter is one, the program loop is terminated. If the loop counter is not one, it is decremented by one and the program loop is repeated.

The loop counter may be read and written under program control. This gives software programs access to the value of the current loop iteration. It also allows for saving and restoring the LC to and from the software stack when nesting DO loops in software. Note that since the LC is only a 13-bit counter, it is zero-extended when read; when written, the top three bits of the source word are ignored. This is shown in Figure 5-3 on page 5-5.