Addressing Modes

4.2.4.3 I/O Short Address (Direct Addressing): <pp>

For the I/O short addressing mode, the address of the operand occupies 6 bits in the instruction operation word and is one-extended. This allows direct access to the last 64 locations in X memory, which contain the on-chip peripheral registers. No registers are used to form the address of the operand. See Figure 4-14 for examples of using the I/O short direct addressing mode.

I/O Short Address Example: MOVE X:<<$FFFB,R3

Assembler syntax: X:<pp>

Additional instruction execution cycles: 0 Additional effective address program words: 0

AA0027

Figure 4-14. Special Addressing: I/O Short Address

4.2.5 Implicit Reference

Some instructions make implicit reference to the program counter (PC), software stack, hardware stack (HWS), loop address register (LA), loop counter (LC), or status register (SR). The implied registers and their use are defined by the individual instruction descriptions. See Appendix A, “Instruction Set Details,“ for more information.

4.2.6 Addressing Modes Summary

Table 4-8 on page 4-24 contains a summary of the addressing modes discussed in the preceding subsections of Section 4.2.

Address Generation Unit

Table 4-8. Addressing Mode Summary

1.The M01 modifier can only be used on the R0/N/M01 or R1/N/M01 register sets

2.Hardware stack reference

3.Program controller register reference

4.Data ALU register reference

5.Address Generation Unit register reference

6.Program memory reference

7.X memory reference

8.Dual X memory read