Data Arithmetic Logic Unit

3.4 Saturation and Data Limiting

DSP algorithms are sometimes capable of calculating values larger than the data precision of the machine when processing real data streams. Normally, a processor would allow the value to overflow when this occurred, but this creates problems when processing real-time signals. The solution is saturation, a technique whereby values that exceed the machine data precision are “clipped,” or converted to the maximum value of the same sign that fits within the given data precision.

Saturation is especially important when data is running through a digital filter whose output goes to a digital-to-analog converter (DAC), since it “clips” the output data instead of allowing arithmetic overflow. Without saturation, the output data may incorrectly switch from a large positive number to a large negative value, which can cause problems for DAC outputs in embedded applications.

The DSP56800 architecture supports optional saturation of results through two limiters found within the data ALU:

•the Data Limiter

•the MAC Output Limiter

The Data Limiter saturates values when data is moved out of an accumulator with a MOVE instruction or parallel move. The MAC Output Limiter saturates the output of the data ALU’s MAC unit.

3.4.1 Data Limiter

The data limiter protects against overflow by selectively limiting when reading an accumulator register as a source operand in a MOVE instruction. When a MOVE instruction specifies an accumulator (F) as a source, and if the contents of the selected source accumulator can be represented in the destination operand size without overflow (that is, the accumulator extension register not in use), the data limiter is enabled but does not saturate, and the register contents are placed onto the CGDB unmodified. If a MOVE instruction is used and the contents of the selected source accumulator cannot be represented without overflow in the destination operand size, the data limiter will substitute a “limited” data value onto the CGDB that has maximum magnitude and the same sign as the source accumulator, as shown in Table 3-4 on page 3-27.

The F0 portion of an accumulator is ignored by the data limiter.

Consider a simple example, shown in Example 3-17.

Example 3-17. Demonstrating the Data Limiter—Positive Saturation

Saturation and Data Limiting

Once the accumulator increments to $8000 in Example 3-17, the positive result can no longer be written to a 16-bit memory location without overflow. So, instead of writing an overflowed value to memory, the value of the most positive 16-bit number, $7fff, is written instead by the data limiter block. Note that the data limiter block does not affect the accumulator; it only affects the value written to memory. In the last instruction, the limiter is disabled because the register is specified as A1.

Consider a second example, shown in Example 3-18 on page 3-27.

Example 3-18. Demonstrating the Data Limiter — Negative Saturation

Once the accumulator decrements to $7FFF in Example 3-18, the negative result can no longer fit into a 16-bit memory location without overflow. So, instead of writing an overflowed value to memory, the value of the most negative 16-bit number, $8000, is written instead by the data limiter block.

Test logic exists in the extension portion of each accumulator register to support the operation of the limiter circuit; the logic detects overflows so that the limiter can substitute one of two constants to minimize errors due to overflow. This process is called “saturation arithmetic.” When limiting does occur, a flag is set and latched in the status register. The value of the accumulator is not changed.

Table 3-4. Saturation by the Limiter Using the MOVE Instruction

It is possible to bypass this limiting feature when reading an accumulator by reading it out through its individual portions.

Figure 3-14 on page 3-28 demonstrates the importance of limiting. Consider the A accumulator with the following 36-bit value to be read to a 16-bit destination:

0000 1.000 0000 0000 0000 0000 0000 0000 0000 (in binary) (+ 1.0 in fractional decimal, $0 8000 0000 in hexadecimal)

If this accumulator is read without the limiting enabled by a MOVE A1,X0 instruction, the 16-bit X0 register after the MOVE instruction would contain the following, assuming signed fractional arithmetic:

1.000 0000 0000 0000(- 1.0 fractional decimal, $8000 in hexadecimal)

Data Arithmetic Logic Unit

This is clearly in error because the value -1.0 in the X0 register greatly differs from the value of +1.0 in the source accumulator. In this case, overflow has occurred. To minimize the error due to overflow, it is preferable to write the maximum (“limited”) value the destination can assume. In this example, the limited value would be:

0.111 1111 1111 1111(+ 0.999969 fractional decimal, $7FFF in hexadecimal)

This is clearly closer to the original value, +1.0, than -1.0 is, and thus introduces less error. Saturation is equally applicable to both integer and fractional arithmetic.

Thus, saturation arithmetic can have a large effect in moving from register A1 to register X0. The instruction MOVE A1,X0 performs a move without limiting, and the instruction MOVE A,X0 performs a move of the same 16 bits with limiting enabled. The magnitude of the error without limiting is 2.0; with limiting it is 0.000031.

*Limiting automatically occurs when the 36-bit operands A and B are read with a MOVE instruction. Note that the contents of the original accumulator are not changed.

Figure 3-14. Example of Saturation Arithmetic

3.4.2 MAC Output Limiter

The MAC output limiter optionally saturates or limits results calculated by data ALU arithmetic operations such as multiply, add, increment, round, and so on.

The MAC Output Limiter can be enabled by setting the SA bit in the OMR register. See Section 5.1.9.3, “Saturation (SA)—Bit 4,” on page 5-11.

Consider a simple example, shown in Example 3-19.

Example 3-19. Demonstrating the MAC Output Limiter

Saturation and Data Limiting

Once the accumulator increments to $7FFF in Example 3-19, the saturation logic in the MAC Output limiter prevents it from growing larger because it can no longer fit into a 16-bit memory location without overflow. So instead of writing an overflowed value to back to the A accumulator, the value of the most positive 32-bit number, $7FFF:FFFF, is written instead as the arithmetic result.

The saturation logic operates by checking 3 bits of the 36-bit result out of the MAC unit: EXT[3], EXT[0], and MSP[15]. When the SA bit is set, these 3 bits determine if saturation is performed on the MAC unit’s output and whether to saturate to the maximum positive value ($7FFF:FFFF) or the maximum negative value ($8000:0000), as shown in Table 3-5.

Table 3-5. MAC Unit Outputs with Saturation Enabled

The MAC Output Limiter not only affects the results calculated by the instruction, but can also affect condition code computation as well. See Appendix A.4.2, “Effects of the Operating Mode Register’s SA Bit,” on page A-11 for more information.

3.4.3 Instructions Not Affected by the MAC Output Limiter

The MAC Output Limiter is always disabled (even if the SA bit is set) when the following instructions are being executed:

•ASLL, ASRR, LSRR

•ASRAC, LSRAC

•IMPY

•MPYSU, MACSU

•AND, OR, EOR

•LSL, LSR, ROL, ROR, NOT

•TST

The CMP is not affected by the OMR’s SA bit except for the case when the first operand is not a register (that is, it is a memory location or an immediate value) and the second operand is the X0, Y0, or Y1 register. In this particular case, the U bit calculation is affected by the SA bit. No other bits are affected by the SA bit for the CMP instruction.