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Fractional and Integer Data ALU Arithmetic |
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Example 3-11. Multiplying Two Unsigned Fractional Values |
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MOVE |
X:FIRST,X0 |
; Get first operand from memory |
ANDC |
#$7FFF,X0 |
; Force first operand to be positive |
MOVE |
X:SECOND,Y0 |
; Get second operand from memory |
MPYSU |
X0,Y0,A |
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TSTW |
X:FIRST |
; Perform final addition if MSB of first operand was a one |
BGE |
OVER |
; If first operan is less that one, jump to OVER |
MOVE |
#$0,B |
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MOVE |
Y0,B1 |
; Move Y0 to B without sign extension |
ADD |
B,A |
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OVER |
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(ASR |
A) |
; Optionally convert to integer result |
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3.3.8 Multi-Precision Operations
The DSP56800 instruction set contains several instructions which simplify extendedand multi-precision mathematical operations. By using these instructions, 64-bit and 96-bit calculations can be performed, and calculations involving different-sized operands are greatly simplified.
3.3.8.1 Multi-Precision Addition and Subtraction
Two instructions, ADC and SBC, assist in performing multi-precision addition (Example 3-12) and subtraction (Example 3-13), such as 64-bit or 96-bit operations.
Example 3-12. 64-Bit Addition
X:$1:X:$0:Y1:Y0 + A2:A1:A0:B1:B0 = A2:A1:A0:B1:B0
(B2 must contain only sign extension before addition begins; that is, bits 35–31 are all 1s or 0s)
MOVE |
X:$21,B |
; Correct sign extension |
MOVE |
X:$20,B0 |
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ADD |
Y,B |
; First 32-bit addition |
MOVE |
X:$0,Y0 |
; Get second 32-bit operand from memory |
MOVE |
X:$1,Y1 |
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ADC |
Y,A |
; Second 32-bit addition |
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Example 3-13. 64-Bit Subtraction
A2:A1:A0:B1:B0 - X:$1:X:$0:Y1:Y0 = A2:A1:A0:B1:B0
(B2 must contain only sign extension before addition begins; that is, bits 35–31 are all 1s or 0s)
MOVE |
X:$21,B |
; Correct sign extension |
MOVE |
X:$20,B0 |
|
SUB |
Y,B |
; First 32-bit subtraction |
MOVE |
X:$0,Y0 |
; Get second 32-bit operand from memory |
MOVE |
X:$1,Y1 |
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SBC |
Y,A |
; Second 32-bit subtraction |
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3.3.8.2 Multi-Precision Multiplication
Two instructions are provided to assist with multi-precision multiplication. When these instructions are used, the multiplier accepts one signed and one unsigned two’s-complement operand. The instructions are:
•MPYSU—multiplication with one signed and one unsigned operand
Data Arithmetic Logic Unit |
3-23 |
Data Arithmetic Logic Unit
•MACSU—multiply-accumulate with one signed and one unsigned operand
The use of these instructions in multi-precision multiplication is demonstrated in Figure 3-13, with corresponding examples shown in Example 3-14, Example 3-15 on page 3-24, and Example 3-16 on page 3-25.
16 Bits
X0
32 Bits
Y1 |
Y0 |
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x
Signed x Unsigned
X0 x Y0
Signed x Signed
X0 x Y1
+
Sign Ext.
A2 |
A1 |
A0 |
B1 |
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48 Bits |
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AA0046 |
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Figure 3-13. Single-Precision Times Double-Precision Signed Multiplication
Example 3-14. Fractional Single-Precision Times Double-Precision Value—Both Signed
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(5 Icyc, 5 Instruction Words) |
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MPYSU |
X0,Y0,A |
; Single Precision times Lower Portion |
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MOVE |
A0,B |
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MOVE |
A1,A0 |
; 16-bit Arithmetic Right Shift |
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MOVE |
A2,A1 |
; (note that A2 contains only sign extension) |
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MAC |
X0,Y1,A |
; Single Precision times Upper Portion |
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; and added to Previous |
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Example 3-15. Integer Single-Precision Times Double-Precision Value—Both Signed |
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(7 Icyc, 7 Instruction Words) |
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MPYSU |
X0,Y0,A |
; Single Precision times Lower Portion |
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MOVE |
A0,B |
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MOVE |
A1,A0 |
; 16-bit Arithmetic Right Shift |
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MOVE |
A2,A1 |
; (note that A2 contains only sign |
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; extension) |
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MAC |
X0,Y1,A |
; Single Precision x Upper Portion and add to Previous |
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ASR |
A |
; Convert result to integer, A2 contains sign extension |
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ROR |
B |
; (52-bit shift of A2:A1:A0:B1) |
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3-24 |
DSP56800 Family Manual |
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Fractional and Integer Data ALU Arithmetic
Example 3-16. Multiplying Two Fractional Double-Precision Values
;
;Signed 32x32 => 64 Multiplication Subroutine
;Parameters:
;R1 = ptr to lowest word of one operand
;R2 = ptr to lowest word of one operand
;R3 = ptr to where results are stored
MULT_S32_X_S32 |
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CLR |
B |
; clears B2 portion |
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; Multiply lwr1 * lwr2 and save lowest 16-bits of result |
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; Operation |
; |
X0 |
Y1 |
Y0 |
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A |
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; --------- |
; ----- |
----- |
----- |
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------------------- |
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MOVE |
X:(R1),Y0 |
; |
--- |
--- |
lwr1 |
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----- |
ANDC |
#CLRMSB,Y0 |
; |
--- |
--- |
lwr1’ |
----- |
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MOVE |
X:(R2)+,Y1 |
; |
--- |
lwr2 |
lwr1’ |
----- |
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MPYSU |
Y0,Y1,A |
; |
--- |
lwr2 |
lwr1’ |
lwr1’.s * lwr2.u |
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TSTW |
X:(R1)+ |
; |
check if MSB set in original lwr1 value |
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BGE |
CORRECT_RES1 |
; |
perform correction if this was true |
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MOVE |
Y1,B1 |
; |
--- |
lwr2 |
lwr1’ |
----- |
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ADD |
B,A |
; |
--- |
lwr2 |
lwr1’ |
lwr1.u * lwr2.u |
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CORRECT_RES1 |
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MOVE |
A0,X:(R3)+ |
; |
--- |
lwr2 |
lwr1’ |
lwr1.u * lwr2.u |
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; Multiply two cross products and save next |
lowest |
16-bits of result |
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; Operation |
; |
X0 |
Y1 |
Y0 |
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A |
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; --------- |
; ----- |
----- |
----- |
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------------------- |
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MOVE |
A1,X:TMP |
; |
(arithmetic |
16-bit right shift of 36-bit accum) |
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MOVE |
A2,A |
; |
---- |
---- |
---- |
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----- |
MOVE |
X:TMP,A0 |
; |
---- |
---- |
---- |
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A = product1 >> 16 |
MOVE |
X:(R1)-,X0 |
; |
upr1 |
lwr2 |
lwr1’ |
A = product1 >> 16 |
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MACSU |
X0,Y1,A |
; |
upr1 |
lwr2 |
lwr1’ |
A+upr1.s*lwr2.u |
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MOVE |
X:(R1),Y1 |
; |
upr1 |
lwr1 |
lwr1’ |
A+upr1.s*lwr2.u |
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MOVE |
X:(R2),Y0 |
; |
upr1 |
lwr1 |
upr2 |
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A+upr1.s*lwr2.u |
MACSU |
Y0,Y1,A |
; |
upr1 |
lwr1 |
upr2 |
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A+upr1.s*lwr2.u+upr2.s*lwr1.u |
MOVE |
A0,X:(R3)+ |
; |
upr1 |
lwr1 |
upr2 |
|
A = result w/ cross prods |
; Multiply upr1 * upr2 and save |
highest 32-bits of result |
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; Operation |
; |
X0 |
Y1 |
Y0 |
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A |
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; --------- |
; ----- |
----- |
----- |
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------------------- |
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MOVE |
A1,X:TMP |
; |
(arithmetic |
16-bit right shift of 36-bit accum) |
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MOVE |
A2,A |
; |
upr1 |
lwr1 |
upr2 |
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----- |
MOVE |
X:TMP,A0 |
; |
upr1 |
lwr1 |
upr2 |
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A = result >> 16 |
MAC |
X0,Y0,A |
; |
upr1 |
lwr1 |
upr2 |
|
A + upr1.s * upr2.s |
MOVE |
A0,X:(R3)+ |
; |
--- |
--- |
--- |
|
----- |
MOVE |
A1,X:(R3)+ |
; |
--- |
--- |
--- |
|
----- |
RTS
;The corresponding algorithm for integer multiplication of 32-bit values
;would be the same as for fractional with the addition of a final arithmetic
;right shift of the 64-bit result.
Data Arithmetic Logic Unit |
3-25 |