Fractional and Integer Data ALU Arithmetic

3.3.4 Logical Operations

For fractional and integer arithmetic, the logical operations (AND, OR, EOR, and bit-manipulation instructions) are performed identically. This means that any DSP56800 logical or bit-field instruction can be used for both fractional and integer values. Typically, logical operations are only performed on integer values, but there is no inherent reason why they cannot be performed on fractional values as well.

Likewise, shifting can be done on both integer and fractional data values. For both of these, an arithmetic left shift of 1 bit corresponds to a multiplication by two. An arithmetic right shift of 1 bit corresponds to a division of a signed value by two, and a logical right shift of 1 bit corresponds to a division of an unsigned value by two.

3.3.5 Multiplication

The multiplication operation is not the same for integer and fractional arithmetic. The result of a fractional multiplication differs in a simple manner from the result of an integer multiplication. This difference amounts to a 1-bit shift of the final result, as illustrated in Figure 3-10. Any binary multiplication of two N-bit signed numbers gives a signed result that is 2N-1 bits in length. This 2N-1 bit result must then be correctly placed into a field of 2N bits to correctly fit into the on-chip registers. For correct fractional multiplication, an extra 0 bit is placed at the LSB to give a 2N bit result. For correct integer multiplication, an extra sign bit is placed at the MSB to give a 2N bit result.

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Figure 3-10. Comparison of Integer and Fractional Multiplication

The MPY, MAC, MPYR, and MACR instructions perform fractional multiplication and fractional multiply-accumulation. The IMPY(16) instruction performs integer multiplication. Section 3.3.5.2, “Integer Multiplication,” explains how to perform integer multiplication.

3.3.5.1 Fractional Multiplication

Figure 3-11 on page 3-20 shows the multiply-accumulation implementation for fractional arithmetic. The multiplication of two, 16-bit, signed, fractional operands gives an intermediate 32-bit, signed, fractional result with the LSB always set to zero. This intermediate result is added to one of the 36-bit accumulators. If rounding is specified in the MPY or MAC instruction (MACR or MPYR), the intermediate results will be rounded to 16 bits before being stored back to the destination accumulator, and the LSP will be set to zero.

36 Bits

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Figure 3-11. MPY Operation—Fractional Arithmetic

3.3.5.2 Integer Multiplication

Two techniques for performing integer multiplication on the DSP core are as follows:

•Using the IMPY(16) instruction to generate a 16-bit result in the MSP of an accumulator

•Using the MPY and MAC instructions to generate a 36-bit full precision result

Each technique has its advantages for different types of computations.

An examination of the instruction set shows that for execution of single precision operations, most often the instructions operate on the MSP (bits 31–16) of the accumulator instead of the LSP (bits 15–0). This is true for the LSL, LSR, ROL, ROR, NOT, INCW, and DECW instructions and others. Likewise, for the parallel MOVE instructions, it is possible to move data to and from the MSP of an accumulator, but this is not true for the LSP. Thus, an integer multiplication instruction that places its result in the MSP of an accumulator allows for more efficient computing. This is the reason why the IMPY(16) instruction places its results in bits 31–16 of an accumulator. The limitation with the IMPY(16) instruction is that the result must fit within 16 bits or there is an overflow.

Figure 3-12 on page 3-21 shows the multiply operation for integer arithmetic. The multiplication of two 16-bit signed integer operands using the IMPY(16) instruction gives a 16-bit signed integer result that is placed in the MSP (A1 or B1) of the accumulator. The corresponding extension register (A2 or B2) is filled with sign extension and the LSP (A0 or B0) remains unchanged.