Data Arithmetic Logic Unit

3.2.2 Accessing an Entire Accumulator

3.2.2.1 Accessing for Data ALU Operations

The complete accumulator is accessed to provide a source, a destination, or both for an ALU or multiplication operation in the data ALU. In this case, the accumulator is written as an entire 36-bit accumulator (F), not as an individual register (F2, F1, or F0). The accumulator registers receive the EXT:MSP:LSP of the multiply-accumulator unit output when used as a destination and supply a source accumulator of the same form. Most data ALU operations specify the 36-bit accumulator registers as source operands, destination operands, or both.

3.2.2.2 Writing an Accumulator with a Small Operand

Automatic sign extension of the 36-bit accumulators is provided when the accumulator is written with a smaller size operand. This can occur when writing F from the CGDB (MOVE instruction) or with the results of certain data ALU operations (for example, ADD, SUB, or TFR from a 16-bit register to a 36-bit accumulator). If a word operand is to be written to an accumulator register (F), the F1 portion of the accumulator is written with the word operand, the LSP is zeroed, and the EXT portion receives sign extension. This is also the case for a MOVE instruction that moves one accumulator to another, but is not the case for a TFR instruction that moves one entire accumulator to another. No sign extension is performed if an individual 16-bit register is written (F1 or F0).

NOTE:

A read of the F1 register in a MOVE instruction is identical to a read of the F accumulator for the case where the extension bits of that accumulator only contain sign-extension information. In this case there is no need for saturation or limiting, so reading the F accumulator produces the same result as reading the F1 register.

3.2.2.3 Extension Registers as Protection Against Overflow

The F2 extension registers offer protection against 32-bit overflow. When the result of an accumulation crosses the MSB of MSP (bit 31 of F), the extension bit of the status register (E) is set. Up to 15 overflows or underflows are possible using these extension bits, after which the sign is lost beyond the MSB of the extension register. When this occurs, the overflow bit (V) in the status register is set. Having an extension register allows overflow during intermediate calculations without losing important information. This is particularly useful during execution of DSP algorithms, when intermediate calculations (but not the final result that is written to memory or to a peripheral) may sometimes overflow.

The logic detection of “extension register in use” is also used to determine when to saturate the value of an accumulator when it is being read onto the CGDB or transferred to any data ALU register. If saturation occurs, the content of the original accumulator is not affected (except if the same accumulator is specified as both source and destination); only the value transferred over the CGDB is limited to a full-scale positive or negative 16-bit value ($7FFF or $8000).

When limiting occurs, a flag is set and latched in the status register (L). The limiting block is explained in more detail in Section 3.4.1, “Data Limiter.”

NOTE:

Limiting will be performed only when the entire 36-bit accumulator register (F) is specified as the source for a parallel data move or a register transfer. It is not performed when F2, F1 or F0 is specified.