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Поволжский государственный технологический университет

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ЦОС_Заочники2013 / Курсовая МПиЦОС 2011 / Справочная информация / ADC&DAC / AD5601_5611_5621.pdf

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AD5601/AD5611/AD5621

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

		1		6	VOUT
			AD5601/
	SYNC
SCLK		2	AD5611/	5	GND
			AD5621
	SDIN	3	TOP VIEW	4	VDD
			(Not to Scale)

06853-003

Figure 3. 6-Lead SC70 Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic

1SYNC

2SCLK

3SDIN

4VDD

5GND

6VOUT

Description

Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register, and data is transferred in on the falling edges of the clocks that follow. The DAC is updated following the 16th clock cycle, unless SYNC is taken high before this edge, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC.

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 30 MHz.

Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the serial clock input.

Power Supply Input. The AD5601/AD5611/AD5621 can be operated from 2.7 V to 5.5 V. VDD should be decoupled to GND. Ground. Ground reference point for all circuitry on the AD5601/AD5611/AD5621.

Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation.

Rev. D | Page 6 of 20

TYPICAL PERFORMANCE CHARACTERISTICS

	1.0
	1.0	VDD = VREF = 5V
		VDD = VREF = 5V
		TA = 25°C
(LSB)	0.5
	0.5

ERRORINL	0
	0
	–0.5
	–0.5
	–1.0
	–1.0
	64		564		1064			1564			2064	2564	3064	3564		4064
										DAC CODE						06853004-
						Figure 4. Typical AD5621 INL
	0.5
	0.5		VDD = VREF = 5V
			VDD = VREF = 5V
	0.4		TA = 25°C
	0.4		TA = 25°C
	0.3


(LSB)	0.2
	0.2
	0.1
ERROR	0.1
ERROR	0
	0
INL	–0.1
	–0.1
	–0.2


	–0.3
	–0.3
	–0.4
	–0.4
	–0.5
	–0.5															005-
	16		116		216		316		416		516	616	716	816	916	005-
	16		116		216		316		416		516	616	716	816	916	06853
										DAC CODE						06853
						Figure 5. Typical AD5611 INL
	0.100
				VDD = VREF = 5V
	0.075			TA = 25°C
				TA = 25°C


	0.050
	0.050
(LSB)	0.025
(LSB)	0.025
ERROR	0
INL	0
	–0.025
	–0.025

	–0.050
	–0.050
	–0.075
	–0.075
	–0.100 4																-006
	–0.100 4				54				104			154		204			-006
											DAC CODE					06853

Figure 6. Typical AD5601 INL

AD5601/AD5611/AD5621

	2.5
	2.5	VDD = VREF = 5V
		VDD = VREF = 5V
(LSB)	2.0	TA = 25°C
	2.0	TA = 25°C
	1.5
ERROR	1.5
ERROR	1.0
	1.0
UNADJUSTED	0.5
	0.5
	0
	0
	–0.5
	–0.5
TOTAL	–1.0
	–1.0
	–1.5
	–1.5
	–2.0
	–2.0
	–2.5
	–2.5

	64	564	1064	1564	2064	2564	3064	3564	4064	06853007-
				DAC CODE						06853007-
		Figure 7. AD5621 Total Unadjusted Error (TUE)
	0.6
	0.6	VDD = VREF = 5V
		VDD = VREF = 5V
(LSB)		TA = 25°C
(LSB)	0.4
ERROR	0.4
ERROR	0.2
UNADJUSTEDTOTAL	0.2
UNADJUSTEDTOTAL	–0.4
	0
	–0.2

	–0.616	116	216	316	416		516	616	716	816	916	06853-008
					DAC CODE							06853-008
		Figure 8. AD5611 Total Unadjusted Error (TUE)
	0.20
		VDD = VREF = 5V
(LSB)	0.15	TA = 25°C
	0.15
	0.10
ERROR	0.10
	0.05
	0.05
UNADJUSTED	0
	0
TOTAL	–0.05
	–0.05
	–0.10
	–0.10
	–0.15												009-
	–0.15
	–0.20
	–0.20		54		104			154		204
	4		54		104			154		204		06853
						DAC CODE						06853

Figure 9. AD5601 Total Unadjusted Error (TUE)

Rev. D | Page 7 of 20

AD5601/AD5611/AD5621
	0.20		VDD = 5V									12	VDD = 3V													VDD = 5V
			VDD = 5V										VDD = 3V													VDD = 5V
	0.15		TA = 25°C										VIH	= DVDD												VIH = DVDD
	0.15											10	VIL = GND													VIL = GND
												10	TA = 25°C													TA = 25°C
	0.10										NUMBER OF DEVICES
DNL ERROR (LSB)	0.05											8
	0.05
	0	0										6
	–0.05											4
												4
	–0.10
	–0.10
	–0.15											2
	–0.15
	–0.20	64	564	1064	1564	2064	2564	3064	3564	06853-010		0	0.05456 0.05527	0.05599	0.05671	0.05742	0.05814		0.05885	0.06710	0.06773	0.06835	0.06897	0.06960	0.07022	0.07084 0.07147 0.07209 0.07271	0.07334
		64	564	1064	1564	2064	2564	3064	3564
					DAC CODE																							06853-013

																		I		(mA)0.06648
																			DD

Figure 10. Typical AD5621 DNL

	0.05	VDD = 5V
		VDD = 5V
	0.04	TA = 25°C
	0.03
(LSB)	0.02
(LSB)	0.01
ERROR	0
ERROR	–0.01
DNL	–0.01
DNL	–0.02
	–0.02
	–0.03
	–0.04
	–0.05	116	216	316	416	516	616	716	816	916	06853-011
	16	116	216	316	416	516	616	716	816	916
					DAC CODE

Figure 11. Typical AD5611 DNL

	0.010	VDD = 5V
	0.008	VDD = 5V
	0.008	TA = 25°C
	0.006
(LSB)	0.004
	0.002

ERROR	0
ERROR	–0.002
DNL	–0.002
DNL	–0.004
	–0.004
	–0.006
	–0.008
	–0.010					06853-012
	4	54	104	154	204
			DAC CODE
			DAC CODE

Figure 13. IDD Histogram (3 V/5 V)

TA = 25°C

VDD = 5V

CH1 = SCLK







	CH2 = VOUT
		06853-014


CH1 = 5V/DIV CH2 = 1V/DIV TIME BASE = 2µs/DIV

Figure 14. Full-Scale Settling Time

		TA = 25°C
		VDD = 5V
	CH1 = SCLK
	CH2 = VOUT
		06853-015
CH1 = 5V/DIV	CH2 = 1V/DIV	TIME BASE = 2µs/DIV

Figure 12. Typical AD5601 DNL

Figure 15. Half-Scale Settling Time

Rev. D | Page 8 of 20

AD5601/AD5611/AD5621

VDD = 5V	VDD
TA = 25°C
CH1
	VOUT = 70mV
CH2		06853-016
CH1 1V, CH2 20mV, TIME BASE = 20µs/DIV		06853-016
CH1 1V, CH2 20mV, TIME BASE = 20µs/DIV

Figure 16. Power-On Reset to 0 V

CH1
VDD	V	= 5V
	DD
	TA = 25°C
CH2
VOUT
CH1 1V, CH2 5V, TIME BASE = 50µs/DIV		06853-017

Figure 17. VDD vs. VOUT

	2.458
	2.458
	2.456
	2.456
	2.454
	2.454
(V)	2.452
	2.452
	2.450
AMPLITUDE	2.448
	2.448
	2.446
	2.446
	2.444
	2.444
	2.442
					TA = 25°C


	2.440				VDD = 5V
					LOAD = 2kΩ AND 220pF
	2.438				CODE 0x2000 TO 0x1FFF
	2.438				CODE 0x2000 TO 0x1FFF
	2.436				10ns/SAMPLE NUMBER			-018


	0	100	200	300		400	500
	0	100	200	300		400	500	06853
			SAMPLE NUMBER					06853

Figure 18. Digital-to-Analog Glitch Energy

VDD = 5V

TA = 25°C

MIDSCALE LOADED

CH1

06853-019

CH1 5µV/DIV

Figure 19. 1/f Noise, 0.1 Hz to 10 Hz Bandwidth

	VDD = 5V
CH1	TA = 25°C
	VOUT
CH2
	CH1 5V, CH2 1V, TIME BASE = 2µs/DIV	06853-020

Figure 20. Exiting Power-Down Mode

	140					3/4 SCALE
						3/4 SCALE
	120		FULL SCALE
	120
	100				MIDSCALE
	100			1/4 SCALE
				1/4 SCALE
	80
(µA)	60
DD	60			ZERO SCALE
DD
I
	40
	20
	0
	0	5	10	15	20	25
			FREQUENCY (MHz)			06853021-
						06853021-

Figure 21. IDD vs. SCLK vs. Code

Rev. D | Page 9 of 20

AD5601/AD5611/AD5621
Hz)	700	VDD = 5V
		VDD = 5V
		TA = 25°C
(nV/	600	TA = 25°C
	600	UNLOADED OUTPUT

DENSITY	500
DENSITY
SPECTRAL	400
	300

NOISE	200		MIDSCALE
	200		FULL SCALE

OUTPUT
	100
		ZERO SCALE
	0		1k	10k	100k	022-
	100		1k	10k	100k	06853
			FREQUENCY (Hz)			06853

Figure 22. Noise Spectral Density

	70
									TA = 25°C
	60	VDD = 5V							TA = 25°C
		VDD = 5V


	50
	50
		VDD = 3V
(µA)	40
	40

DD	30
I	30
	20
	20
	10
	10
	0										-023
	0	2000	4000	6000	8000	10000	12000	14000		16000	-023
	0	2000	4000	6000	8000	10000	12000	14000		16000	06853
				DIGITAL INPUT CODE							06853

Figure 23. Supply Current vs. Digital Input Code

0.8

VDD = 5V

0.6TA = 25°C

DAC LOADED WITH ZERO-SCALE CODE

		0.4
	(V)	0.2
	OUT	0.2
	OUT
	V	0.0
		0.0

–0.2
–0.2

–0.4		DAC LOADED WITH FULL-SCALE CODE
–15	–10		–5	0	5	10	15	06853-024
–0.6

I (mA)

Figure 24. Sink and Source Capability

	0.3	VDD = 5V			AD5621 MAX INL ERROR
	0.2
	0.1	AD5611 MAX INL ERROR					AD5601 MAX INL ERROR
(LSB)	0
(LSB)	–0.1	AD5611 MIN INL ERROR
INL ERROR	–0.1	AD5611 MIN INL ERROR
	–0.2						AD5601 MIN INL ERROR
	–0.3
	–0.3
	–0.4
	–0.5				AD5621 MIN INL ERROR
	–0.5
	–0.6		–20	0	20	40	60	80	100	120
	–40		–20	0	20	40	60	80	100	120
					TEMPERATURE (°C)					06853025-

Figure 25. INL vs. Temperature (5 V)

	0.08	VDD = 5V
	0.07	VDD = 5V
	0.06	AD5621 MAX DNL ERROR
	0.05	AD5621 MAX DNL ERROR
	0.05
	0.04
(LSB)	0.03		AD5611 MAX DNL ERROR
	0.02		AD5611 MAX DNL ERROR
	0.02
	0.01
ERROR	0.01
	0
	–0.01
DNL	–0.02	AD5611 MIN DNL ERROR		AD5601 MAX DNL ERROR
DNL	–0.03			AD5601 MIN DNL ERROR
	–0.04
	–0.05
	–0.06			AD5621 MIN DNL ERROR
	–0.07			AD5621 MIN DNL ERROR
	–0.07
	–0.08	10	60	110	160	06853-026
	–40	10	60	110	160
			TEMPERATURE (°C)

Figure 26. DNL vs. Temperature (5 V)

	0.00149
	0.00149	VDD = 5V
		VDD = 5V
(LSB)	0.00099				AD5621 ZERO-CODE ERROR
					AD5621 ZERO-CODE ERROR



								AD5611 ZERO-CODE ERROR
ERROR	0.00049							AD5601 ZERO-CODE ERROR
	0.00049							AD5601 FULL-SCALE ERROR


	–0.00001
	–0.00001

			AD5611 FULL-SCALE ERROR
			AD5621 FULL-SCALE ERROR										027-
	–0.00051
	–0.00051		–20	0	–20		40	60	80	100	120	140
	–40		–20	0	–20		40	60	80	100	120	140	06853
						TEMPERATURE (°C)							06853

Figure 27. Zero-Code Error and Full-Scale Error vs. Temperature

Rev. D | Page 10 of 20

	1.5
R(LSB)	1.3				AD5621 MAX TUE
R(LSB)	1.1
	1.1
ERRO	0.9
ERRO	0.7
UNADJUSTED	0.1			AD5601 MAX TUE
	0.5			AD5601 MAX TUE
	0.3			AD5611 MAX TUE
	0.3
TOTAL	–0.1				AD5601 MIN TUE
	–0.1
	–0.3				AD5611 MIN TUE
					AD5621 MIN TUE
	–0.5–40	–20	0	20	40	60	80	100	120	140	06853-028
				TEMPERATURE (°C)							06853-028

Figure 28. Total Unadjusted Error (TUE) vs. Temperature (5 V)

	1.5
	1.4
	1.3
	1.2
(mV)	1.1
	1.0				VDD = 5V
	0.9
ERROR	0.9
	0.8
	0.7				VDD = 3V
OFFSET	0.7
	0.6
	0.6
	0.5
	0.4
	0.4
	0.3
	0.2
	0.1
	0										-029
	–40	–20	0	20	40	60	80	100	120	140	-029
	–40	–20	0	20	40	60	80	100	120	140	06853
				TEMPERATURE (°C)							06853

Figure 29. Offset Error vs. Temperature (3 V/5 V Supply)

	0
	–0.002
	–0.004					VDD = 5V
	–0.004
(%FSR)	–0.006
(%FSR)
ERROR	–0.008
ERROR	–0.010
GAIN	–0.010				VDD = 3V
					VDD = 3V
	–0.012
	–0.012
	–0.014
	–0.016										-030
	–40	–20	0	20	40	60	80	100	120	140	-030
	–40	–20	0	20	40	60	80	100	120	140	06853
				TEMPERATURE (°C)							06853

Figure 30. Gain Error vs. Temperature (3 V/5 V Supply)

				AD5601/AD5611/AD5621
	0.10
	0.09
	0.08
	0.07			VDD = 5V
(mA)	0.06
(mA)	0.05
DD				V	DD	= 3V
I	0.04				DD
	0.04
	0.03
	0.02
	0.01
	0
	–40	–20	0	20		40	60	80	100	120	140
				TEMPERATURE (°C)							06853031-

Figure 31. Supply Current vs. Temperature (3 V/5 V Supply)

	0.4	TA = 25°C
	0.4
	0.2	AD5621 MAX INL ERROR
(LSB)			AD5611 MAX INL ERROR			AD5601 MAX INL ERROR
			AD5611 MAX INL ERROR
	0
ERROR	0
			AD5601 MIN INL ERROR
	–0.2	AD5611 MIN INL ERROR
INL	–0.2	AD5611 MIN INL ERROR
INL
	–0.4
		AD5621 MIN INL ERROR
	–0.6							-032
	2.7		3.2	3.7	4.2	4.7	5.2	-032
				SUPPLY VOLTAGE (V)				06853

Figure 32. INL vs. Supply Voltage at 25°C

	0.10							TA = 25°C
	0.09							TA = 25°C
	0.08
	0.07
	0.06
	0.05
(LSB)	0.04				AD5621 MAX DNL ERROR
	0.03				AD5621 MAX DNL ERROR
	0.03
	0.02			AD5611 MAX DNL ERROR
ERROR	0.01			AD5611 MAX DNL ERROR
	0.01
	0
	–0.01
	–0.02		AD5611 MIN DNL ERROR
DNL	–0.02		AD5611 MIN DNL ERROR
DNL	–0.03		AD5601 MAX DNL ERROR
	–0.04		AD5601 MIN DNL ERROR
	–0.05		AD5601 MIN DNL ERROR
	–0.05
	–0.06
	–0.07				AD5621 MIN DNL ERROR
	–0.08				AD5621 MIN DNL ERROR
	–0.08
	–0.09									06853-033
	–0.10	3.2	3.7	4.2	4.7	5.2	5.7	6.2	6.7
	2.7	3.2	3.7	4.2	4.7	5.2	5.7	6.2	6.7
				SUPPLY VOLTAGE (V)

Figure 33. DNL vs. Supply Voltage at 25°C

Rev. D | Page 11 of 20

AD5601/AD5611/AD5621
	1.5	T = 25°C
		A
(LSB)	1.3	AD5621 MAX TUE
		AD5621 MAX TUE
	1.1
ERROR	1.1
ERROR	0.9
	0.9
UNADJUSTED	0.7
UNADJUSTED	0.5
	0.5
	0.3	AD5611 MAX TUE
	0.3	AD5621 MIN TUE
TOTAL		AD5621 MIN TUE
TOTAL	0.1
	0.1
	–0.1	AD5601 MAX TUE
		AD5611 MIN TUE
		AD5601 MIN TUE

–0.3						034-06853
–0.3
2.7	3.2	3.7	4.2	4.7	5.2

SUPPLY VOLTAGE (V)

Figure 34. Total Unadjusted Error (TUE) vs. Supply Voltage at 25°C

	0.0010	TA = 25°C
		TA = 25°C		AD5621 ZERO-CODE ERROR
				AD5621 ZERO-CODE ERROR
	0.0008
	0.0006
(LSB)	0.0004			AD5601 FULL-SCALE ERROR
ERROR	0.0002			AD5611 ZERO-CODE ERROR
				AD5611 ZERO-CODE ERROR

				AD5601 ZERO-CODE ERROR
	0
				AD5611 FULL-SCALE ERROR
	–0.0002			AD5621 FULL-SCALE ERROR
				AD5621 FULL-SCALE ERROR
	–0.0004	3.2	3.7	4.2	4.7	5.2	5.7	6.2	6.7	06853-035
	2.7	3.2	3.7	4.2	4.7	5.2	5.7	6.2	6.7
				SUPPLY VOLTAGE (V)

Figure 35. Zero-Code Error and Full-Scale Error vs. Supply Voltage at 25°C

	0.10
	TA = 25°C
	0.09
	0.08
	0.07
(mA)	0.06
(mA)	0.05
DD
I	0.04
	0.04
	0.03
	0.02
	0.01						-036
	0						-036
	0						06853
	2.7	3.2	3.7	4.2	4.7	5.2	06853

SUPPLY VOLTAGE (V)

Figure 36. Supply Current vs. Supply Voltage at 25°C

	450		TA = 25°C	SCLK/SDIN
			TA = 25°C	SCLK/SDIN
	400			INCREASING			SCLK/SDIN
				VDD = 5V			SCLK/SDIN
	350			VDD = 5V			DECREASING
	350						VDD = 5V
	300
							SCLK/SDIN
(µA)	250						INCREASING
(µA)							VDD = 3V
DD	200
I	200
	150
	100
	50
	0		SCLK/SDIN DECREASING VDD = 3V
	0	0	1	2	3	4	5	6
					VLOGIC (V)			06853037-

Figure 37. SCLK/SDIN vs. Logic Voltage

Rev. D | Page 12 of 20

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