ЦОС_Заочники2013 / Курсовая МПиЦОС 2011 / Справочная информация / ADC&DAC / cs4226-f2
.pdf
CS4226
Surround Sound Codec
Features
!Stereo 20-bit A/D converters
!Six 20-bit D/A converters
!S/PDIF receiver
– AC-3 & MPEG auto-detect capability
!108 dB DAC signal-to-noise ratio (EIAJ)
!Mono 20-bit A/D converter
!Programmable Input gain & output attenuation
!On-chip anti-aliasing and output smoothing filters
!De-emphasis for 32 kHz, 44.1 kHz, 48 kHz
Description
The CS4226 is a single-chip codec providing stereo an- alog-to-digital and six digital-to-analog converters using Delta-Sigma conversion techniques. This +5V device also contains volume control independently selectable for each of the six D/A channels. An S/PDIF receiver is included as a digital input channel. Applications include Dolby Pro-logic , Dolby Digital AC-3, THX and DTS home theater systems, DSP based car audio systems, and other multi-channel applications.
The CS4226 is packaged in a 44-pin plastic TQFP.
ORDERING INFORMATION |
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CS4226-KQ |
-10° to +70° C |
44-pin TQFP |
CS4226-BQ |
-40° to +85° C |
44-pin TQFP |
CS4226-DQ |
-40° to +85° C |
44-pin TQFP |
CDB4226 |
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Evaluation Board |
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SCL/CCLK SDA/CDOUT AD1/CDIN AD0/CS |
I2C/SPI |
VD+ |
VA+ |
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PDN |
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Control Port |
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Voltage |
CMOUT |
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Reference |
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DAC#1 |
Volume |
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AOUT1 |
LRCK |
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Control |
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DAC#2 |
Volume |
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SCLK |
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AOUT2 |
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Control |
Analog Low Pass and |
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SDIN1 |
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Audio Data Interface |
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Digital Filters |
DAC#3 |
Volume |
Output Stage |
AOUT3 |
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SDIN2 |
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Control |
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SDIN3 |
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DAC#4 |
Volume |
AOUT4 |
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Control |
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DAC#5 |
Volume |
AOUT5 |
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Control |
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SDOUT1 |
Serial |
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DAC#6 |
Volume |
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AOUT6 |
SDOUT2 |
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Mono |
Control |
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Digital Filters |
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AINAUX |
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ADC |
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OVL/ERR |
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MUX |
Left |
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Input Gain |
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AIN1L |
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Input MUX |
AIN1R |
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ADC |
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Right |
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AIN2L/FREQ0 |
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DEM |
DEM |
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ADC |
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AIN2R/FREQ1 |
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AIN3L/AUTODATA |
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Clock Osc/ |
PLL |
S/PDIF RX/Auxiliary Input |
AIN3R/AUDIO |
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AGND1 |
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Divider |
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AGND2 |
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CLKOUT |
XTI |
XTO |
FILT HOLD/RUBIT |
LRCKAUX/RX3 |
RX1 DGND1 DGND2 |
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DATAUX/RX4 |
SCLKAUX/RX2 |
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Copyright Cirrus Logic, Inc. 2003 |
MAR ‘03 |
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www.cirrus.com |
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(All Rights Reserved) |
DS188F2 |
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1 |
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CS4226 |
TABLE OF CONTENTS |
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1 CHARACTERISTICS/SPECIFICATIONS .................................................................................. |
4 |
SPECIFIED OPERATING CONDITIONS ................................................................................. |
4 |
ABSOLUTE MAXIMUM RATINGS ........................................................................................... |
4 |
ANALOG CHARACTERISTICS ................................................................................................ |
5 |
SWITCHING CHARACTERISTICS .......................................................................................... |
7 |
SWITCHING CHARACTERISTICS - CONTROL PORT........................................................... |
8 |
S/PDIF RECEIVER CHARACTERISTICS ................................................................................ |
9 |
DIGITAL CHARACTERISTICS ................................................................................................. |
9 |
2 FUNCTIONAL DESCRIPTION ................................................................................................ |
11 |
2.1 Overview .......................................................................................................................... |
11 |
2.2 Analog Inputs ................................................................................................................... |
11 |
2.2.1 Line Level Inputs ................................................................................................. |
11 |
2.2.2 Adjustable Input Gain .......................................................................................... |
12 |
2.2.3 High Pass Filter ................................................................................................... |
12 |
2.3 Analog Outputs ................................................................................................................ |
12 |
2.3.1 Line Level Outputs .............................................................................................. |
12 |
2.3.2 Output Level Attenuator ...................................................................................... |
12 |
2.4 Clock Generation ............................................................................................................. |
13 |
2.4.1 Clock Source ....................................................................................................... |
13 |
2.4.2 Master Clock Output ........................................................................................... |
14 |
2.4.3 Synchronization ................................................................................................... |
14 |
2.5 Digital Interfaces .............................................................................................................. |
14 |
2.5.1 Audio DSP Serial Interface Signals ..................................................................... |
14 |
2.5.2 Audio DSP Serial Interface Formats ................................................................... |
15 |
2.5.3 Auxiliary Audio Port Signals ................................................................................ |
17 |
Contacting Cirrus Logic Support |
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For all product questions and inquiries contact a Cirrus Logic Sales Representative. |
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To find one nearest you go to www.cirrus.com |
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IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other parts of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or quota needs to be obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign Trade Law and is to be exported or taken out of the PRC.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COMPONENTS AND PERSONAL OR AUTOMOTIVE SAFETY OR SECURITY DEVICES). INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
I2C is a registered trademark of Philips Semiconductor. Purchase of I2C Components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use those components in a standard I2C system.
DTS is a registered trademark of the Digital Theater Systems, Inc.
Dolby, Dolby Digital, AC-3, AAC, and Pro Logic are registered trademarks of Dolby Laboratories, Inc.
THX is a registered trademark of Lucasfilms Ltd.
2 |
DS188F2 |
CS4226
2.5.4 Auxiliary Audio Port Formats .............................................................................. |
17 |
2.5.5 S/PDIF Receiver ................................................................................................. |
17 |
2.5.6 AC-3/MPEG Auto Detection ................................................................................ |
18 |
2.6 Control Port Signals ......................................................................................................... |
18 |
2.6.1 SPI Mode ............................................................................................................ |
18 |
2.6.2 I2C Mode ............................................................................................................. |
19 |
2.6.3 Control Port Bit Definitions .................................................................................. |
19 |
2.7 Power-up/Reset/Power Down Mode ............................................................................... |
20 |
2.8 DAC Calibration ............................................................................................................... |
20 |
2.9 De-Emphasis ................................................................................................................... |
20 |
2.10 HOLD Function .............................................................................................................. |
21 |
2.11 Power Supply, Layout, and Grounding .......................................................................... |
21 |
2.12 ADC and DAC Filter Response Plots ............................................................................ |
22 |
3 REGISTER DESCRIPTION ..................................................................................................... |
24 |
4 PIN DESCRIPTION .................................................................................................................. |
32 |
5 PARAMETER DEFINITIONS ................................................................................................... |
36 |
6 PACKAGE DIMENSIONS ....................................................................................................... |
37 |
LIST OF FIGURES |
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Figure 1. Recommended Connection Diagram............................................................................. |
10 |
Figure 2. Optional Line Input Buffer .............................................................................................. |
11 |
Figure 3. Butterworth Filter Examples........................................................................................... |
13 |
Figure 4. Audio DSP and Auxiliary Port Data Input Formats ........................................................ |
15 |
Figure 5. Audio DSP Port Data Output Formats ........................................................................... |
15 |
Figure 6. One data line modes...................................................................................................... |
16 |
Figure 7. Control Port Timing, SPI mode ...................................................................................... |
18 |
Figure 8. Control Port Timing, I2C Mode....................................................................................... |
19 |
Figure 9. De-emphasis Curve ....................................................................................................... |
20 |
Figure 10. 20-bit ADC Filter Response ......................................................................................... |
22 |
Figure 11. 20-bit ADC Passband Ripple ....................................................................................... |
22 |
Figure 12. 20-bit ADC Transition Band ......................................................................................... |
22 |
Figure 13. DAC Frequency Response .......................................................................................... |
22 |
Figure 14. DAC Passband Ripple ................................................................................................. |
22 |
Figure 15. DAC Transition Band ................................................................................................... |
22 |
LIST OF TABLES |
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Table 1. Single-ended vs Differential Input Pin Assignments ....................................................... |
11 |
Table 2. High Pass Filter Characteristics ..................................................................................... |
12 |
Table 3. DSP Serial Interface Ports ............................................................................................. |
15 |
Table 4. S/PDIF Receiver Status Outputs .................................................................................... |
17 |
DS188F2 |
3 |
CS4226
1 CHARACTERISTICS/SPECIFICATIONS
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25°C.)
SPECIFIED OPERATING CONDITIONS
(AGND, DGND = 0V, all voltages with respect to 0V.)
Parameter |
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Symbol |
Min |
Nom |
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Max |
Units |
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Power Supplies |
Digital |
VD+ |
4.75 |
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5.0 |
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5.25 |
V |
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|(VA+)-(VD+)|<0.4V |
Analog |
VA+ |
4.75 |
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5.0 |
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5.25 |
V |
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Operating Ambient Temperature |
CS4226-KQ |
TA |
-10 |
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- |
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70 |
°C |
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CS4226-BQ |
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-40 |
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- |
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85 |
°C |
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CS4226-DQ |
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-40 |
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- |
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85 |
°C |
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ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0V, all voltages with respect to 0V.) |
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Parameter |
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Symbol |
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Min |
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Typ |
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Max |
Units |
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Power Supplies |
Digital |
VD+ |
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-0.3 |
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- |
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6.0 |
V |
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Analog |
VA+ |
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-0.3 |
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- |
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6.0 |
V |
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Input Current |
(Note 1) |
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- |
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±10 |
mA |
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Analog Input Voltage |
(Note 2) |
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-0.7 |
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- |
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(VA+)+0.7 |
V |
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Digital Input Voltage |
(Note 2) |
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-0.7 |
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- |
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(VD+)+0.7 |
V |
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Ambient Temperature |
(Power Applied) |
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-55 |
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+125 |
°C |
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Storage Temperature |
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-65 |
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+150 |
°C |
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WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
Notes: 1. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause SCR latch-up.
2. The maximum over or under voltage is limited by the input current.
4 |
DS188F2 |
CS4226
ANALOG CHARACTERISTICS (Full Scale Input Sine wave, 990.52 Hz; Fs = 44.1 kHz (PLL in use); Measurement Bandwidth is 20 Hz to 20 kHz, unless specified otherwise.)
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CS4226-KQ |
CS4226-BQ/-DQ |
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Parameter |
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Symbol |
Min |
Typ |
Max |
Min |
Typ |
Max |
Units |
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Analog Input Characteristics - Minimum gain |
setting (0 |
dB) Differential Input; unless otherwise specified. |
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ADC Resolution |
Stereo Audio channels |
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16 |
- |
20 |
16 |
- |
20 |
Bits |
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Mono channel |
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16 |
- |
20 |
16 |
- |
20 |
Bits |
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Total Harmonic Distortion |
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THD |
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0.003 |
- |
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0.003 |
- |
% |
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Dynamic Range |
(A weighted, Stereo) |
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92 |
95 |
- |
90 |
93 |
- |
dB |
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(unweighted, Stereo) |
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- |
92 |
- |
- |
90 |
- |
dB |
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(A weighted, Mono) |
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89 |
- |
- |
87 |
- |
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dB |
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Total Harmonic |
-1 dB, Stereo |
(Note 3) |
THD+N |
- |
-88 |
-82 |
- |
-86 |
-80 |
dB |
Distortion + Noise |
-1 dB, Mono |
(Note 1) |
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- |
- |
-72 |
- |
- |
-70 |
dB |
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Interchannel Isolation |
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- |
90 |
- |
- |
90 |
- |
dB |
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Interchannel Gain Mismatch |
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- |
0.1 |
- |
- |
0.1 |
- |
dB |
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Programmable Input Gain Span |
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8 |
9 |
10 |
8 |
9 |
10 |
dB |
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Gain Step Size |
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2.7 |
3 |
3.3 |
2.7 |
3 |
3.3 |
dB |
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Offset Error (with high pass filter) |
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- |
- |
0 |
- |
- |
0 |
LSB |
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Full Scale Input Voltage (Single Ended): |
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0.90 |
1.0 |
1.10 |
0.90 |
1.0 |
1.10 |
Vrms |
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Gain Drift |
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- |
100 |
- |
- |
100 |
- |
ppm/°C |
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Input Resistance |
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(Note 4) |
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10 |
- |
- |
10 |
- |
- |
kΩ |
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Input Capacitance |
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- |
- |
15 |
- |
- |
15 |
pF |
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CMOUT Output Voltage |
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- |
2.3 |
- |
- |
2.3 |
- |
V |
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A/D Decimation Filter Characteristics |
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Passband |
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(Note 5) |
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0.02 |
- |
20.0 |
0.02 |
- |
20.0 |
kHz |
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Passband Ripple |
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- |
- |
0.01 |
- |
- |
0.01 |
dB |
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Stopband |
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(Note 5) |
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27.56 |
- |
5617.2 |
27.56 |
- |
5617.2 |
kHz |
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Stopband Attenuation |
(Note 6) |
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80 |
- |
- |
80 |
- |
- |
dB |
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Group Delay (Fs = Output Sample Rate) |
(Note 7) |
tgd |
- |
15/Fs |
- |
- |
15/Fs |
- |
s |
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Group Delay Variation vs. Frequency |
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∆ tgd |
- |
- |
0 |
- |
- |
0 |
µs |
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Notes: 3. Referenced to typical full-scale differential input voltage (2Vrms).
4.Input resistance is for the input selected. Non-selected inputs have a very high (>1MΩ) input resistance. The input resistance will vary with gain value selected, but will always be greater than the min. value specified
5.Filter characteristics scale with output sample rate.
6.The analog modulator samples the input at 5.6448 MHz for an output sample rate of 44.1 kHz. There is no rejection of input signals which are multiples of the sampling frequency (n × 5.6448 MHz ±20.0 kHz where n = 0,1,2,3...).
7.Group delay for Fs = 44.1 kHz, tgd = 15/44.1 kHz = 340 µs
DS188F2 |
5 |
CS4226
ANALOG CHARACTERISTICS (Continued)
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CS4226-KQ |
CS4226-BQ |
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Parameter |
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Symbol |
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Units |
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Min |
Typ |
Max |
Min |
Typ |
Max |
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High Pass Filter Characteristics |
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Frequency Response: |
-3 dB |
(Note 5) |
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- |
3.4 |
- |
- |
3.4 |
- |
Hz |
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-0.13 dB |
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- |
20 |
- |
- |
20 |
- |
Hz |
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Phase Deviation |
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@ 20 Hz |
(Note 5) |
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- |
10 |
- |
- |
10 |
- |
Deg. |
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Passband Ripple |
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- |
- |
0 |
- |
- |
0 |
dB |
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Analog Output Characteristics - Minimum Attenuation, 10 kΩ, 100 pF load; unless otherwise specified. |
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|
|
DAC Resolution |
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16 |
- |
20 |
16 |
- |
20 |
Bits |
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Signal-to-Noise/Idle |
|
(DAC muted, A weighted) |
|
101 |
108 |
- |
99 |
106 |
- |
dB |
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Channel Noise |
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||
Dynamic Range |
(DAC not muted, A weighted) |
|
93 |
98 |
- |
91 |
96 |
- |
dB |
||
(DAC not muted, unweighted) |
|
- |
95 |
- |
- |
93 |
- |
dB |
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Total Harmonic Distortion |
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THD |
- |
0.003 |
- |
- |
0.003 |
- |
% |
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Total Harmonic Distortion + Noise |
(Stereo) |
THD+N |
- |
-88 |
-83 |
- |
-86 |
-81 |
dB |
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Interchannel Isolation |
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- |
90 |
- |
- |
90 |
- |
dB |
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Interchannel Gain Mismatch |
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|
- |
0.1 |
- |
- |
0.1 |
- |
dB |
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Attenuation Step Size |
|
(All Outputs) |
|
0.7 |
1 |
1.3 |
0.7 |
1 |
1.3 |
dB |
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Programmable Output Attenuation Span |
|
-84 |
-86 |
- |
-84 |
-86 |
- |
dB |
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Offset Voltage |
|
(relative to CMOUT) |
|
- |
±15 |
- |
- |
±15 |
- |
mV |
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Full Scale Output Voltage |
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|
0.92 |
1.0 |
1.08 |
0.92 |
1.0 |
1.08 |
Vrms |
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Gain Drift |
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- |
100 |
- |
- |
100 |
- |
ppm/°C |
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Out-of-Band Energy |
|
(Fs/2 to 2Fs) |
|
- |
-60 |
- |
- |
-60 |
- |
dBFs |
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Analog Output Load |
|
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Resistance: |
|
10 |
- |
- |
10 |
- |
- |
kΩ |
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|
Capacitance: |
|
- |
- |
100 |
- |
- |
100 |
pF |
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|||
Combined Digital and Analog Filter Characteristics |
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Frequency Response |
|
10 Hz to 20 kHz |
|
- |
±0.1 |
- |
- |
±0.1 |
- |
dB |
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||
Deviation from Linear Phase |
|
|
- |
±0.5 |
- |
- |
±0.5 |
- |
Deg. |
||
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||
Passband: to 0.01 dB corner |
(Notes 8, 9) |
|
0 |
- |
20.0 |
0 |
- |
20.0 |
kHz |
||
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|
Passband Ripple |
|
|
(Note 9) |
|
- |
- |
±0.01 |
- |
- |
±0.01 |
dB |
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|
Stopband |
|
|
(Notes 8, 9) |
|
24.1 |
- |
- |
24.1 |
- |
- |
kHz |
|
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Stopband Attenuation |
|
|
(Note 10) |
|
70 |
- |
- |
70 |
- |
- |
dB |
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||
Group Delay (Fs = Input Word Rate) |
(Note 5) |
tgd |
- |
16/Fs |
- |
- |
16/Fs |
- |
s |
||
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||
Analog Loopback Performance |
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||||
Signal-to-noise Ratio (CCIR-2K weighted, -20 dB input) |
CCIR-2K |
- |
71 |
- |
- |
71 |
- |
dB |
|||
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Power Supply |
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|
Power Supply Current |
|
Operating |
|
- |
90 |
113 |
- |
90 |
115 |
mA |
|
|
|
|
Power Down |
|
- |
1 |
3 |
- |
1 |
3 |
mA |
|
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|
||
Power Supply Rejection |
(1 kHz, 10 mVrms) |
|
- |
45 |
- |
- |
45 |
- |
dB |
||
Notes: 8. The passband and stopband edges scale with frequency. For input word rates, Fs, other than 44.1 kHz, the 0.01 dB passband edge is 0.4535×Fs and the stopband edge is 0.5465×Fs.
9.Digital filter characteristics.
10.Measurement bandwidth is 10 Hz to 3 Fs.
6 |
DS188F2 |
CS4226
SWITCHING CHARACTERISTICS (Outputs loaded with 30 pF)
|
|
|
|
Parameter |
|
|
Symbol |
|
|
Min |
|
Typ |
|
|
Max |
|
Units |
|||||||||||||||
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|||
|
Audio ADC's & DAC's Sample Rate |
|
|
Fs |
|
|
4 |
|
|
|
- |
|
50 |
|
|
kHz |
||||||||||||||||
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|||||
|
XTI Frequency |
|
(XTI = 256, 384, or 512 Fs) |
|
|
|
1.024 |
|
|
|
- |
|
26 |
|
|
MHz |
||||||||||||||||
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||
|
XTI Pulse Width High |
XTI = 512 Fs |
|
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10 |
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|
- |
|
- |
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ns |
|||||||||||||
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|
XTI = 384 Fs |
|
|
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21 |
|
|
|
- |
|
- |
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|
ns |
|||||||||
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|
XTI = 256 Fs |
|
|
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|
31 |
|
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- |
|
- |
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ns |
|||||||||
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||
|
XTI Pulse Width Low |
XTI = 512 Fs |
|
|
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|
10 |
|
|
|
- |
|
- |
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|
ns |
|||||||||||||
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|
XTI = 384 Fs |
|
|
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21 |
|
|
|
- |
|
- |
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|
ns |
|||||||||
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XTI = 256 Fs |
|
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31 |
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- |
|
- |
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ns |
|||||||||
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|||||
|
PLL Clock Recovery Frequency RX, XTI, LRCK, LRCKAUX |
|
|
|
|
30 |
|
|
|
- |
|
50 |
|
|
kHz |
|||||||||||||||||
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XTI Jitter Tolerance |
|
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|
- |
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500 |
|
- |
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|
ps |
||||||||
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PDN |
Low Time |
|
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|
|
(Note 11) |
|
|
|
|
500 |
|
|
|
- |
|
- |
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ns |
|||||||
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|
SCLK Falling Edge to SDOUT Output Valid |
|
(DSCK = 0) |
tdpd |
|
|
- |
|
|
|
- |
|
1 |
|
|
|
|
ns |
||||||||||||||
|
|
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|
|
------------------- + 20 |
|
|||||||||||||||||||||||
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|
(384)Fs |
|
|
||||
|
LRCK edge to MSB valid |
|
|
|
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|
|
tlrpd |
|
|
- |
|
|
|
- |
|
40 |
|
|
ns |
||||||||||
|
SDIN Setup Time Before SCLK Rising Edge |
|
(DSCK=0) |
tds |
|
|
- |
|
|
|
- |
|
25 |
|
|
ns |
||||||||||||||||
|
SDIN Hold Time After SCLK Rising Edge |
|
(DSCK=0) |
tdh |
|
|
- |
|
|
|
- |
|
25 |
|
|
ns |
||||||||||||||||
|
Master Mode |
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||||
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SCLK Period |
|
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tsck |
|
|
1 |
|
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|
- |
|
- |
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|
ns |
|||||||||
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|
|
------------------- |
|
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|||||||||||||||
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(256)Fs |
|
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|
||||
|
SCLK Falling to LRCK Edge |
|
(DSCK=0) |
tmslr |
|
|
- |
|
|
|
±10 |
|
- |
|
|
|
ns |
|||||||||||||||
|
SCLK Duty Cycle |
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- |
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50 |
|
- |
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% |
||||||||
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Slave Mode |
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||||
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SCLK Period |
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tsckw |
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1 |
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- |
|
- |
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ns |
|||||||||
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|
------------------- |
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|||||||||||||||
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(128)Fs |
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||||
|
SCLK High Time |
|
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tsckh |
|
|
40 |
|
|
|
- |
|
- |
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|
ns |
|||||||||
|
SCLK Low Time |
|
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tsckl |
|
|
40 |
|
|
|
- |
|
- |
|
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|
ns |
|||||||||
|
SCLK Rising to LRCK Edge |
|
|
|
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|
|
(DSCK=0) |
tlrckd |
|
|
20 |
|
|
|
- |
|
- |
|
|
|
ns |
|||||||||
|
LRCK Edge to SCLK Rising |
|
|
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|
|
(DSCK=0) |
tlrcks |
|
|
40 |
|
|
|
- |
|
- |
|
|
|
ns |
|||||||||
Notes: 11. After powering up the CS4226, |
|
|
should be held low until the power supply is settled. |
|
||||||||||||||||||||||||||||
PDN |
|
|||||||||||||||||||||||||||||||
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LRCK |
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LR C K A UX |
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||
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|
|
t sck |
(input) |
t lrckd |
|
t lrcks |
|
t sckh |
|
tsckl |
|
|||||||||||
|
|
SCLK* |
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||||||||||||||||||||
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|||||||||||||||||
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||||
|
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SCLKAUX* |
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S C LK * |
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|||||
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(output) |
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||||||
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|
S C L KA U X * |
|
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||||||
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|||
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t mslr |
|
(input) |
|
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|
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t sckw |
|
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|
||||||
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|||||||
|
|
LRCK |
|
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SDIN1 |
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||||||||||||||
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||||||||||||
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||||||
|
|
LRCKAUX |
|
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SDIN2 |
|
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||||
|
|
(output) |
|
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|
SDIN3 |
|
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||||
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|
D AT AU X |
|
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|
t lrpd |
t ds |
|
t dh |
|
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t dp d |
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SDOUT1 |
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S D O U T 1 |
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M S B |
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MSB-1 |
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SDOUT2 |
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S D O U T 2 |
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*S C LK , SC LK AU X sh ow n for D SC K = 0 and ASC K = 0. |
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S C LK & S CL KA U X inverted for D SC K = 1 a nd A SC K = 1 , respectively. |
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Audio Ports Master Mode Timing |
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Audio Ports Slave Mode and Data I/O timing |
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DS188F2 |
7 |
CS4226
SWITCHING CHARACTERISTICS - CONTROL PORT (Inputs: logic 0 = DGND, logic 1 =
VD+, CL = 30 pF)
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Parameter |
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Symbol |
Min |
Max |
Units |
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SPI Mode (SPI/I2C = 0) |
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CCLK Clock Frequency |
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fsck |
- |
6 |
MHz |
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CS |
High Time Between Transmissions |
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tcsh |
1.0 |
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s |
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CS |
Falling to CCLK Edge |
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tcss |
20 |
|
ns |
CCLK Low Time |
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tscl |
66 |
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ns |
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CCLK High Time |
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tsch |
66 |
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ns |
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CDIN to CCLK Rising Setup Time |
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tdsu |
40 |
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ns |
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CCLK Rising to DATA Hold Time |
(Note 12) |
tdh |
15 |
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ns |
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CCLK Falling to CDOUT stable |
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tpd |
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45 |
ns |
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Rise Time of CDOUT |
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tr1 |
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25 |
ns |
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Fall Time of CDOUT |
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tf1 |
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25 |
ns |
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Rise Time of CCLK and CDIN |
(Note 13) |
tr2 |
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100 |
ns |
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Fall Time of CCLK and CDIN |
(Note 13) |
tf2 |
|
100 |
ns |
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Notes: 12. Data must be held for sufficient time to bridge the transition time of CCLK.
13. For FSCK < 1 MHz
C S |
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t css |
t scl |
t s ch |
C C L K |
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t r2 |
t f2 |
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C D IN |
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t d s u |
t dh |
t csh
t pd
C D O U T
8 |
DS188F2 |
CS4226
SWITCHING CHARACTERISTICS - CONTROL PORT (Inputs: logic 0 = DGND, logic 1 =
VD+, CL = 30 pF)
Parameter |
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Symbol |
Min |
Max |
Units |
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I2C® Mode (SPI/I2C = 1) |
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SCL Clock Frequency |
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fscl |
- |
100 |
kHz |
Bus Free Time Between Transmissions |
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tbuf |
4.7 |
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µs |
Start Condition Hold Time (prior to first clock pulse) |
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thdst |
4.0 |
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µs |
Clock Low Time |
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tlow |
4.7 |
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µs |
Clock High Time |
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thigh |
4.0 |
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µs |
Setup Time for Repeated Start Condition |
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tsust |
4.7 |
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µs |
SDA Hold Time from SCL Falling |
(Note 14) |
thdd |
0 |
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µs |
SDA Setup Time to SCL Rising |
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tsud |
250 |
|
ns |
Rise Time of Both SDA and SCL Lines |
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tr |
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1 |
µs |
Fall Time of Both SDA and SCL Lines |
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tf |
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300 |
ns |
Setup Time for Stop Condition |
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tsusp |
4.7 |
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µs |
Notes: 14. Data must be held for sufficient time to bridge the 300 ns transition time of SCL
S/PDIF RECEIVER CHARACTERISTICS (RX1, RX2, RX3, RX4 pins only)
Parameter |
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Symbol |
Min |
Typ |
Max |
Units |
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Input Resistance |
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ZN |
- |
10 |
- |
kΩ |
Input Voltage |
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VTH |
200 |
- |
- |
mVpp |
Input Hysteresis |
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VHYST |
- |
50 |
- |
mV |
Input Sample Frequency |
|
FS |
30 |
- |
50 |
kHz |
CLKOUT Jitter |
(Note 15) |
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- |
200 |
- |
ps RMS |
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CLKOUT Duty Cycle (high time/cycle time) |
(Note 16) |
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40 |
50 |
60 |
% |
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Notes: 15. CLKOUT Jitter is for 256×FS selected as output frequency measured from falling edge to falling edge. Jitter is greater for 384×Fs and 512×Fs as selected output frequency.
16. For CLKOUT frequency equal to 1×Fs, 384×Fs, and 512×Fs. See Master Clock Output section.
DIGITAL CHARACTERISTICS
|
Parameter |
Symbol |
Min |
Typ |
Max |
Units |
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High-level Input Voltage |
(except RX1) |
VIH |
2.8 |
- |
(VD+)+0.3 |
V |
Low-level Input Voltage |
(except RX1) |
VIL |
-0.3 |
- |
0.8 |
V |
High-level Output Voltage at I0 = -2.0 mA |
VOH |
(VD+)-1.0 |
- |
- |
V |
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Low-level Output Voltage at I0 = 2.0 mA |
VOL |
- |
- |
0.4 |
V |
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Input Leakage Current |
(Digital Inputs) |
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- |
- |
10 |
µA |
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Output Leakage Current |
(High-Impedance Digital Outputs) |
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- |
- |
10 |
µA |
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DS188F2 |
9 |
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CS4226 |
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F e rrite Bea d |
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2.0 Ω |
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+ 5 V |
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S u p p ly |
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+ 1 µ F |
0 .1 µF |
+ 1 µF |
0 .1 µF |
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19 |
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40 |
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V A + |
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V D + |
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To O ptional |
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16 |
C M O U T |
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2 1 |
A N A L O G |
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1 µ F |
+ |
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A O U T 1 |
F ILT E R |
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Input and |
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O utput B uffers |
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2 2 |
A N A L O G |
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1 0 µF |
* |
14 |
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A O U T 2 |
F ILT E R |
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A IN 1 L |
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r |
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1 0 µF |
* |
13 |
A IN 1 R |
CS 4226 |
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u ffe |
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2 3 |
A N A L O G |
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B |
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1 0 µF |
* |
11 |
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A O U T 3 |
F ILT E R |
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u t |
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A IN 2L/F R E Q 0 |
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l In p |
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1 0 µF |
* |
12 |
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na |
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A IN 2R /F R E Q 1 |
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ptio |
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2 4 |
A N A L O G |
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O |
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1 0 µF |
* |
10 |
A IN 3 L/AU T O D A TA |
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A O U T 4 |
F ILT E R |
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m |
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F ro |
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10 µ F |
* |
9 |
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A IN 3 R /A U D IO |
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2 5 |
A N A L O G |
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1 0 µF |
* |
15 |
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A O U T 5 |
F ILT E R |
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A IN A U X |
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R S |
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27 |
D E M |
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R S |
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2 |
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H O LD /R U B IT |
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2 6 |
A N A L O G |
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R S |
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42 |
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R X 1 |
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A O U T 6 |
F ILT E R |
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1 0 0 pF |
† |
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D igital |
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R S |
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3 |
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A ud io |
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1 |
D A T A U X /R X 4 |
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S C L/C C LK |
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S ou rce |
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4 |
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1 0 0 pF |
† |
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S D A /C D O U T |
M icroco ntro ller |
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6 |
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A D 0/C S |
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R S |
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44 |
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5 |
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LR C K A U X /R X 3 |
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A D 1/C D IN |
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† |
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10 0 pF |
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3 4 |
R D |
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S D IN 1 |
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RS |
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43 |
S C LK A U X /R X 2 |
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3 3 |
R D |
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† |
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S D IN 2 |
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1 0 0 pF |
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3 2 |
R D |
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S D IN 3 |
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M ode |
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8 |
P D N |
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3 6 |
R S |
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S etting |
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7 |
I 2 C /S P I |
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S D O U T 1 |
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3 5 |
R S |
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R S |
= 5 0 Ω |
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S D O U T 2 |
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A udio |
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3 7 |
R S |
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R D |
= 4 7 5 Ω |
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D S P |
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LR C K |
R |
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3 8 |
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A ll unus ed digital inp u ts |
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S C L K |
S |
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sh ou ld b e tie d to D G N D . |
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3 1 |
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A ll un us e d ana lo g inp u ts |
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C L K O U T |
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3 0 |
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sh ou ld b e le ft flo atin g . |
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O V L/E R R |
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* O ptional if an alo g inp uts |
A G N D 1 , 2 D G N D 1, 2 |
F IL T |
X T O |
X T I |
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b ia se d to w ith in 1 % |
of |
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2 9 R X2 ** 2 8 |
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C M O U T |
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18 2 0 |
41 3 9 |
1 7 |
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† O nly needed w he n inpu ts |
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R F IL T |
R X1 ** |
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** |
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256, |
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a re used for S /P D IF. |
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1xF s |
384, |
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Loop Current |
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512xF s |
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N orm al |
High |
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C 1** |
C 2** |
C 1 |
4 0 |
pF |
40 |
p F |
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C FILT |
15 nF |
180 n F |
C F IL T |
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C R IP |
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C 2 |
1 0 |
pF |
40 |
p F |
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R FILT |
4 3 kΩ |
3.3 k Ω |
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R X1 |
3 0 0 k Ω |
sho rt |
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C RIP |
1.5 nF |
1 8 nF |
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R X2 |
1 0 M Ω |
open |
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Figure 1. Recommended Connection Diagram |
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10 |
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DS188F2 |