Architecture rtl of reg is

signal n1,n2,m1,m2,m3,m4:bit_vector(1 to 2);

signal n3:bit_vector(1 to 8);

begin

d1: n1(1)<=not D1;d2:n1(2)<= not D2;

d3: n2(1)<=not n1(1); d4:n2(2)<= not n1(2);

d5: Q1(1)<=not n3(1);d6:Q1(2)<= not n3(2);

d7: Q1(3)<=not n3(3);d8: Q1(4)<=not n3(4);

d9: Q2(1)<=not n3(5);d10:Q2(2)<=not n3(6);

d11:Q2(3)<=not n3(7);d12:Q2(4)<=n3(8);

d13:dcrtt port map(RES(1),n2(1),CLK(1),m1(1),n3(1));

d14:dcrtt port map(RES(1),m1(1),CLK(1),m2(1),n3(2));

d15:dcrtt port map(RES(1),m2(1),CLK(1),m3(1),n3(3));

d16:dcrtt port map(RES(1),m3(1),CLK(1),m4(1),n3(4));

d17:dcrtt port map(RES(2),n2(2),CLK(2),m1(2),n3(5));

d18:dcrtt port map(RES(2),m1(2),CLK(2),m2(2),n3(6));

d19:dcrtt port map(RES(2),m2(2),CLK(2),m3(2),n3(7));

d20:dcrtt port map(RES(2),m3(2),CLK(2),m4(2),n3(8));

end RTL;

Architecture alg of reg is

signal int1,int2:bit_vector(1 to 4);

begin

process(Q1,Q2,D1,D2,CLK,RES)

begin

if RES(1)='1' then Q1<="0000";

else if CLK(1)='1' and not CLK(1)'stable then int1(1)<=D1;int1(2)<=Q1(1);int1(3)<=Q1(2);int1(4)<=Q1(3);

else Q1(1)<=int1(1);Q1(2)<=int1(2);Q1(3)<=int1(3);Q1(4)<=int1(4); end if;

end if;

if RES(2)='1' then Q2<="0000";

else if CLK(2)='1' and not CLK(2)'stable then int2(1)<=D2;int2(2)<=Q2(1);int2(3)<=Q2(2);int2(4)<=Q2(3);

else Q2(1)<=int2(1);Q2(2)<=int2(2);Q2(3)<=int2(3);Q2(4)<=int1(4);end if;

end if;

end process;

end ALG;

6.Процедурное моделирование

library elements;

use elements.all;

entity REG is

port(q1,q2:inout bit_vector(1 to 4);c:in bit_vector(1 to 2);d1,d2:in bit;r:in bit_vector(1 to 2));

end REG;

architecture ALG of REG is

signal int1,int2:bit_vector(1 to 4);

signal c :bit_vector(1 to 2);

begin

process(q1,q2,d1,d2,c,r)

begin

if r(1)='1' then q1<="0000";

else if c(1)='1' and not c(1)'stable then int1(1)<=d1;int1(2)<=q1(1);int1(3)<=q1(2);int1(4)<=q1(3);

else q1(1)<=int1(1);q1(2)<=int1(2);q1(3)<=int1(3);q1(4)<=int1(4); end if;

end if;

if r(2)='1' then q2<="0000";

else if c(2)='1' and not c(2)'stable then int2(1)<=d2;int2(2)<=q2(1);int2(3)<=q2(2);int2(4)<=q2(3);

else q2(1)<=int2(1);q2(2)<=int2(2);q2(3)<=int2(3);q2(4)<=int1(4);end if;

end if;

end process;

end ALG;

entity test_REG is

end test_REG;

use std.textio.all;

architecture st of test_REG is

signal d1,d2 : bit;

signal r: bit_vector (1 to 2);

signal q1: bit_vector (1 to 4);

signal q2: bit_vector (1 to 4);

signal c: bit_vector (1 to 2);

component REG port (

q1:in bit_vector(1 to 4);

q2:in bit_vector(1 to 4);

c:in bit_vector(1 to 2);

d1,d2:in bit;

r:in bit_vector(1 to 2));

end component;

begin

device:REG port map(q1,q2,c,d1,d2,r);

c(1)<= '0','1'after 10ns ,'0'after 20ns,'1'after 30ns,'0'after 40ns,'1'after 50ns,'0'after 60ns;

c(2)<= '0','1'after 10ns ,'0'after 20ns,'1'after 30ns,'0'after 40ns,'1'after 50ns,'0'after 60ns;

r(1)<= '1','0'after 10ns,'1'after 50ns,'0'after 60ns;

r(2)<= '1','0'after 10ns,'1'after 50ns,'0'after 60ns;

d1<= '0','1'after 10ns, '0'after 20ns;

d2<= '0','1'after 10ns, '0'after ns;

Lag:process

variable l:line;

begin

write (l,"t c1 c2 r1 r2 d1 d2 q1(1) q1(2) q1(3) q1(4) q2(1) q2(2) q2(3) q2(4)");

writeline(output,l);

wait;end process;

Wri:process

variable t:time;

variable l:line;

begin t:=now;

write(l,t);write(l," ");write(l,c(1)); write(l," ");

write (l,c(2));write(l," ");write(l,r(1));write(l," ");

write (l,r(2)); write(l," ");write(l,d1);write(l," ");

write (l,d2); write (l," ");write(l,q1(1));write(l," ");

write (l,q1(2)); write (l," ");write(l,q1(3));write (l," ");

write (l,q1(4)); write(l," "); write(l,q2(1)); write(l," ");

write (l,q2(2)); write(l," "); write(l,q2(3)); write(l," ");

write (l,q2(4));

writeline(output,l);

wait for 10ns;

end process;

end st;

Содержание bat файла:

vhdl kursov.vhd

link kursov kursov test_REG

sv 50ns kursov

ТАБЛИЦА ИСТИННОСТИ

time	C1	C2	R1	R2	D1	D2	Q1(1)	Q1(2)	Q1(3)	Q1(4)	Q2(1)	Q2(2)	Q2(3)	Q2(4)
0n	0	0	1	1	0	0	0	0	0	0	0	0	0	0
10n	0	0	0	0	1	1	1	0	0	0	1	0	0	0
20n	1	1	0	0	0	1	0	1	0	0	1	1	0	0
30n	0	0	0	0	0	1	0	0	1	0	1	1	1	0
40n	1	1	0	0	0	1	0	0	0	1	1	1	1	1
50n	0	0	1	1	0	0	0	0	0	0	0	0	0	0