Процедурное моделирование.
project.vhd
library model;
use model.all;
use std.textio.all;
entity project is end project;
architecture behavior of project is
component REG23_ALG
port(c,ec,r:in bit;q:out bit_vector(0 to 7);cout:out bit);
end component;
component REG23_RTL
port(c,ec,r:in bit;q1:out bit_vector(0 to 7);cout1:out bit);
end component;
component REG23_STR
port(c,ec,r:in bit;q2:out bit_vector(0 to 7);cout2:out bit);
end component;
for all: REG23_ALG use entity model.REG23(ALG);
for all: REG23_RTL use entity model.REG23(RTL);
for all: REG23_STR use entity model.REG23(STR);
signal c,ec,r,cout_alg,cout_rtl,cout_str:bit;
signal q_alg,q_rtl,q_str:bit_vector(0 to 7);
begin
process
begin
c<='0','1' after 5ns,'0' after 10ns, '1' after 15ns,'0' after 20ns,'1' after 25ns,
'0' after 30ns,'1' after 35ns,'0' after 40ns,'1' after 45ns,'0' after 50ns,
'1' after 55ns,'0' after 60ns,'1' after 65ns,'0' after 70ns,'1' after 75ns,
'0' after 80ns,'1' after 85ns,'0' after 90ns,'1' after 95ns,'0' after 100ns,
'1' after 105ns,'0' after 110ns,'1' after 115ns,'0' after 120ns,
'0' after 125ns,'1' after 130ns,'0' after 135ns,'1' after 140ns,'0' after 145ns,
'1' after 150ns,'0' after 155ns,'1' after 160ns,'0' after 165ns,'1' after 170ns,'0' after 175ns;
ec<='0','1' after 15ns,'0' after 25ns,'1' after 45ns,'0' after 65ns,'1' after 85ns,'0' after 105ns,
'1' after 125ns,'0' after 145ns,'1' after 165ns;
r<='0' after 0ns,'1' after 5ns;
wait;
end process;
d1:REG23_ALG port map(c,ec,r,q_alg,cout_alg);
d2:REG23_RTL port map(c,ec,r,q_rtl,cout_rtl);
d3:REG23_STR port map(c,ec,r,q_str,cout_str);
process
variable l:line;
variable t:time;
begin
t:=now;
if t=0ns then
write (l,"c ec r q_alg cout_alg q_rtl cout_rtl q_str cout_str Time");
writeline(output,l);
end if;
write(l,c); write(l," ");
write(l,ec); write(l," ");
write(l,r); write(l," ");
write(l,q_alg); write(l," ");
write(l,cout_alg); write(l," ");
write(l,q_rtl); write(l," ");
write(l,cout_rtl); write(l," ");
write(l,q_str); write(l," ");
write(l,cout_str); write(l," ");
write(l,t); write(l," ");
writeline(output,l);
wait for 5ns;
end process;
end behavior;
model1.bat
vhdl bibl.vhd >bibl.txt
vhdl model.vhd >model.txt
vhdl project.vhd >project.txt
link project project project > link.txt
sv 180ns project > test.txt
Результат процедурного моделирования.
c ec r q_alg cout_alg q_rtl cout_rtl q_str cout_str
0 0 0 10000000 0 11111111 1 11111111 1 0ns
0 0 0 10000000 1 10000000 1 10000000 1 5ns
1 0 1 10000000 1 10000000 1 10000000 1 10ns
0 0 1 01000000 1 01000000 1 01000000 1 15ns
1 1 1 01000000 1 01000000 1 01000000 1 20ns
0 1 1 01000000 1 01000000 1 01000000 1 25ns
1 0 1 01000000 1 01000000 1 01000000 1 30ns
0 0 1 00100000 1 00100000 1 00100000 1 35ns
1 0 1 00100000 1 00100000 1 00100000 1 40ns
0 0 1 00010000 1 00010000 1 00010000 1 45ns
1 1 1 00010000 1 00010000 1 00010000 1 50ns
0 1 1 00010000 1 00010000 1 00010000 1 55ns
1 1 1 00010000 1 00010000 1 00010000 1 60ns
0 1 1 00010000 1 00010000 1 00010000 1 65ns
1 0 1 00010000 1 00010000 1 00010000 1 70ns
0 0 1 00001000 0 00001000 0 00001000 0 75ns
1 0 1 00001000 0 00001000 0 00001000 0 80ns
0 0 1 00000100 0 00000100 0 00000100 0 85ns
1 1 1 00000100 0 00000100 0 00000100 0 90ns
0 1 1 00000100 0 00000100 0 00000100 0 95ns
1 1 1 00000100 0 00000100 0 00000100 0 100n
0 1 1 00000100 0 00000100 0 00000100 0 105n
1 0 1 00000100 0 00000100 0 00000100 0 110n
0 0 1 00000010 0 00000010 0 00000010 0 115n
1 0 1 00000010 0 00000010 0 00000010 0 120n
0 0 1 00000001 0 00000001 0 00000001 0 125n
0 1 1 00000001 0 00000001 0 00000001 0 130n
1 1 1 00000001 0 00000001 0 00000001 0 135n
0 1 1 00000001 0 00000001 0 00000001 0 140n
1 1 1 00000001 0 00000001 0 00000001 0 145n
0 0 1 10000000 1 10000000 1 10000000 1 150n
1 0 1 10000000 1 10000000 1 10000000 1 155n
0 0 1 01000000 1 01000000 1 01000000 1 160n
1 0 1 01000000 1 01000000 1 01000000 1 165n
0 1 1 00100000 1 00100000 1 00100000 1 170n
1 1 1 00100000 1 00100000 1 00100000 1 175n
0 1 1 00100000 1 00100000 1 00100000 1 180n