- •Pin Configuration
- •Features
- •Description
- •Pin Descriptions
- •Port B (PB5..PB0)
- •Analog Pins
- •Internal Oscillators
- •ATtiny15L Architectural Overview
- •The General-purpose Register File
- •The ALU – Arithmetic Logic Unit
- •The Flash Program Memory
- •The Program and Data Addressing Modes
- •Register Direct, Single-register Rd
- •Register Indirect
- •Register Direct, Two Registers Rd and Rr
- •I/O Direct
- •Relative Program Addressing, RJMP and RCALL
- •Constant Addressing Using the LPM Instruction
- •Subroutine and Interrupt Hardware Stack
- •The EEPROM Data Memory
- •Memory Access and Instruction Execution Timing
- •I/O Memory
- •The Status Register – SREG
- •Reset and Interrupt Handling
- •ATtiny15L Reset Sources
- •Power-on Reset
- •External Reset
- •Brown-out Detection
- •Watchdog Reset
- •MCU Status Register – MCUSR
- •Internal Voltage Reference
- •Voltage Reference Enable Signals and Start-up Time
- •Interrupt Handling
- •Interrupt Response Time
- •The General Interrupt Mask Register – GIMSK
- •The General Interrupt Flag Register – GIFR
- •The Timer/Counter Interrupt Mask Register – TIMSK
- •The Timer/Counter Interrupt Flag Register – TIFR
- •External Interrupt
- •Pin Change Interrupt
- •The MCU Control Register – MCUCR
- •Sleep Modes
- •Idle Mode
- •ADC Noise Reduction Mode
- •Power-down Mode
- •Tunable Internal RC Oscillator
- •The System Clock Oscillator Calibration Register – OSCCAL
- •Internal PLL for Fast Peripheral Clock Generation
- •Timer/Counters
- •The Timer/Counter0 Prescaler
- •The Timer/Counter1 Prescaler
- •The Special Function IO Register – SFIOR
- •The 8-bit Timer/Counter0
- •The Timer/Counter0 Control Register – TCCR0
- •The Timer Counter 0 – TCNT0
- •The 8-bit Timer/Counter1
- •The Timer/Counter1 Control Register – TCCR1
- •The Timer/Counter1 – TCNT1
- •Timer/Counter1 Output Compare RegisterA – OCR1A
- •Timer/Counter1 in PWM Mode
- •Timer/Counter1 Output Compare RegisterB – OCR1B
- •The Watchdog Timer
- •The Watchdog Timer Control Register – WDTCR
- •EEPROM Read/Write Access
- •The EEPROM Address Register – EEAR
- •The EEPROM Data Register – EEDR
- •The EEPROM Control Register – EECR
- •Preventing EEPROM Corruption
- •The Analog Comparator
- •The Analog Comparator Control and Status Register – ACSR
- •The Analog-to-digital Converter, Analog Multiplexer and Gain Stages
- •Feature List:
- •Operation
- •Prescaling and Conversion Timing
- •ADC Noise Canceler Function
- •The ADC Multiplexer Selection Register – ADMUX
- •The ADC Control and Status Register – ADCSR
- •The ADC Data Register – ADCL and ADCH
- •ADLAR = 0:
- •Scanning Multiple Channels
- •ADC Noise-canceling Techniques
- •ADC Characteristics
- •I/O Port B
- •Alternative Functions of Port B
- •The Port B Data Register – PORTB
- •The Port B Data Direction Register – DDRB
- •The Port B Input Pins Address – PINB
- •PORT B as General Digital I/O
- •Alternate Functions of Port B
- •Memory Programming
- •Program and Data Memory Lock Bits
- •Fuse Bits
- •Signature Bytes
- •Calibration Byte
- •Programming the Flash
- •High-voltage Serial Programming
- •High-voltage Serial Programming Algorithm
- •High-voltage Serial Programming Characteristics
- •Low-voltage Serial Downloading
- •Low-voltage Serial Programming Algorithm
- •Data Polling
- •Low-voltage Serial Programming Characteristics
- •Electrical Characteristics
- •Absolute Maximum Ratings
- •DC Characteristics – Preliminary Data
- •Typical Characteristics – PRELIMINARY DATA
- •ATtiny15L Register Summary
- •Ordering Information
Pin Descriptions
VCC
Supply voltage pin
GND
Ground pin
Port B (PB5..PB0)
Port B is a 6-bit I/O port. PB4..0 are I/O pins that can provide internal pull-ups (selected for each bit). PB5 is input or opendrain output. The use of pin PB5 is defined by a fuse and the special function associated with this pin is external Reset. The port pins are tri-stated when a reset condition becomes active, even if the clock is not running.
Port B also accommodates analog I/O pins. The Port B pins with alternate functions are shown in Table 1.
Table 1. Port B Alternate Functions
Port Pin |
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Alternate Function |
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MOSI (Data Input Line for Memory Downloading) |
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PB0 |
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AREF (ADC Voltage Reference) |
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AIN0 (Analog Comparator Positive Input) |
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MISO (Data Output Line for Memory Downloading) |
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PB1 |
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OC1A (Timer/Counter PWM Output) |
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AIN1 (Analog Comparator Negative Input) |
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SCK (Serial Clock Input for Serial Programming) |
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PB2 |
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INT0 (External Interrupt0 Input) |
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ADC1 (ADC Input Channel 1) |
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T0 (Timer/Counter0 External Counter Input) |
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PB3 |
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ADC2 (ADC Input Channel 2) |
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PB4 |
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ADC3 (ADC Input Channel 3) |
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(External Reset Pin) |
PB5 |
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RESET |
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ADC0 (ADC Input Channel 0) |
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Analog Pins
Up to four analog inputs can be selected as inputs to analog-to-digital converter (ADC).
Internal Oscillators
The internal oscillator provides a clock rate of nominally 1.6 MHz for the system clock (CK). Due to large initial variation (0.8 MHz -1.6 MHz) of the internal oscillator, a tuning capability is built in. Through an 8-bit control register, OSCCAL, the system clock rate can be tuned with less than 1% steps of the nominal clock.
There is an internal PLL that provides a 16x clock rate locked to the system clock (CK) for the use of the Peripheral Timer/Counter1. The nominal frequency of this peripheral clock, PCK, is 25.6 MHz.
4 |
ATtiny15L |
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