
- •Pin Configuration
- •Features
- •Description
- •Pin Descriptions
- •Port B (PB5..PB0)
- •Analog Pins
- •Internal Oscillators
- •ATtiny15L Architectural Overview
- •The General-purpose Register File
- •The ALU – Arithmetic Logic Unit
- •The Flash Program Memory
- •The Program and Data Addressing Modes
- •Register Direct, Single-register Rd
- •Register Indirect
- •Register Direct, Two Registers Rd and Rr
- •I/O Direct
- •Relative Program Addressing, RJMP and RCALL
- •Constant Addressing Using the LPM Instruction
- •Subroutine and Interrupt Hardware Stack
- •The EEPROM Data Memory
- •Memory Access and Instruction Execution Timing
- •I/O Memory
- •The Status Register – SREG
- •Reset and Interrupt Handling
- •ATtiny15L Reset Sources
- •Power-on Reset
- •External Reset
- •Brown-out Detection
- •Watchdog Reset
- •MCU Status Register – MCUSR
- •Internal Voltage Reference
- •Voltage Reference Enable Signals and Start-up Time
- •Interrupt Handling
- •Interrupt Response Time
- •The General Interrupt Mask Register – GIMSK
- •The General Interrupt Flag Register – GIFR
- •The Timer/Counter Interrupt Mask Register – TIMSK
- •The Timer/Counter Interrupt Flag Register – TIFR
- •External Interrupt
- •Pin Change Interrupt
- •The MCU Control Register – MCUCR
- •Sleep Modes
- •Idle Mode
- •ADC Noise Reduction Mode
- •Power-down Mode
- •Tunable Internal RC Oscillator
- •The System Clock Oscillator Calibration Register – OSCCAL
- •Internal PLL for Fast Peripheral Clock Generation
- •Timer/Counters
- •The Timer/Counter0 Prescaler
- •The Timer/Counter1 Prescaler
- •The Special Function IO Register – SFIOR
- •The 8-bit Timer/Counter0
- •The Timer/Counter0 Control Register – TCCR0
- •The Timer Counter 0 – TCNT0
- •The 8-bit Timer/Counter1
- •The Timer/Counter1 Control Register – TCCR1
- •The Timer/Counter1 – TCNT1
- •Timer/Counter1 Output Compare RegisterA – OCR1A
- •Timer/Counter1 in PWM Mode
- •Timer/Counter1 Output Compare RegisterB – OCR1B
- •The Watchdog Timer
- •The Watchdog Timer Control Register – WDTCR
- •EEPROM Read/Write Access
- •The EEPROM Address Register – EEAR
- •The EEPROM Data Register – EEDR
- •The EEPROM Control Register – EECR
- •Preventing EEPROM Corruption
- •The Analog Comparator
- •The Analog Comparator Control and Status Register – ACSR
- •The Analog-to-digital Converter, Analog Multiplexer and Gain Stages
- •Feature List:
- •Operation
- •Prescaling and Conversion Timing
- •ADC Noise Canceler Function
- •The ADC Multiplexer Selection Register – ADMUX
- •The ADC Control and Status Register – ADCSR
- •The ADC Data Register – ADCL and ADCH
- •ADLAR = 0:
- •Scanning Multiple Channels
- •ADC Noise-canceling Techniques
- •ADC Characteristics
- •I/O Port B
- •Alternative Functions of Port B
- •The Port B Data Register – PORTB
- •The Port B Data Direction Register – DDRB
- •The Port B Input Pins Address – PINB
- •PORT B as General Digital I/O
- •Alternate Functions of Port B
- •Memory Programming
- •Program and Data Memory Lock Bits
- •Fuse Bits
- •Signature Bytes
- •Calibration Byte
- •Programming the Flash
- •High-voltage Serial Programming
- •High-voltage Serial Programming Algorithm
- •High-voltage Serial Programming Characteristics
- •Low-voltage Serial Downloading
- •Low-voltage Serial Programming Algorithm
- •Data Polling
- •Low-voltage Serial Programming Characteristics
- •Electrical Characteristics
- •Absolute Maximum Ratings
- •DC Characteristics – Preliminary Data
- •Typical Characteristics – PRELIMINARY DATA
- •ATtiny15L Register Summary
- •Ordering Information

Timer/Counters
The ATtiny15L provides two general-purpose 8-bit Timer/Counters. The Timer/Counters have separate prescaling selection from separate 10-bit prescalers. The Timer/Counter0 uses internal clock (CK) as the clock time base. The Timer/Counter1 may use either the internal clock (CK) or the fast peripheral clock (PCK) as the clock time base.
The Timer/Counter0 Prescaler
Figure 18 shows the Timer/Counter prescaler.
Figure 18. Timer/Counter0 Prescaler
CK |
10-BIT T/C PRESCALER |
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CLEAR |
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CK/8 |
CK/64 |
CK/256 |
CK/1024 |
PSR0 |
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T0 |
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0 |
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CS00
CS01
CS02
TIMER/COUNTER0 CLOCK SOURCE
TCK0
The four prescaled selections are: CK/8, CK/64, CK/256 and CK/1024, where CK is the oscillator clock. CK, external source and stop, can also be selected as clock sources. Setting the PSR10 bit in SFIOR resets the prescaler. This allows the user to operate with a predictable prescaler.
The Timer/Counter1 Prescaler
Figure 19 shows the Timer/Counter1 prescaler. For Timer/Counter1 the clock selections are: PCK, PCK/2, PCK/4, PCK/8, CK (=PCK/16), CK/2, CK/4, CK/8,CK/16, CK/32, CK/64, CK/128, CK/256, CK/512, CK/1024 and stop. The clock options are described in Table 12 on page 30 and the Timer/Counter1 Control Register (TCCR1). Setting the PSR1 bit in the SFIOR register resets the 10-bit prescaler. This allows the user to operate with a predictable prescaler.
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ATtiny15L |
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