- •Pin Configuration
- •Features
- •Description
- •Pin Descriptions
- •Port B (PB5..PB0)
- •Analog Pins
- •Internal Oscillators
- •ATtiny15L Architectural Overview
- •The General-purpose Register File
- •The ALU – Arithmetic Logic Unit
- •The Flash Program Memory
- •The Program and Data Addressing Modes
- •Register Direct, Single-register Rd
- •Register Indirect
- •Register Direct, Two Registers Rd and Rr
- •I/O Direct
- •Relative Program Addressing, RJMP and RCALL
- •Constant Addressing Using the LPM Instruction
- •Subroutine and Interrupt Hardware Stack
- •The EEPROM Data Memory
- •Memory Access and Instruction Execution Timing
- •I/O Memory
- •The Status Register – SREG
- •Reset and Interrupt Handling
- •ATtiny15L Reset Sources
- •Power-on Reset
- •External Reset
- •Brown-out Detection
- •Watchdog Reset
- •MCU Status Register – MCUSR
- •Internal Voltage Reference
- •Voltage Reference Enable Signals and Start-up Time
- •Interrupt Handling
- •Interrupt Response Time
- •The General Interrupt Mask Register – GIMSK
- •The General Interrupt Flag Register – GIFR
- •The Timer/Counter Interrupt Mask Register – TIMSK
- •The Timer/Counter Interrupt Flag Register – TIFR
- •External Interrupt
- •Pin Change Interrupt
- •The MCU Control Register – MCUCR
- •Sleep Modes
- •Idle Mode
- •ADC Noise Reduction Mode
- •Power-down Mode
- •Tunable Internal RC Oscillator
- •The System Clock Oscillator Calibration Register – OSCCAL
- •Internal PLL for Fast Peripheral Clock Generation
- •Timer/Counters
- •The Timer/Counter0 Prescaler
- •The Timer/Counter1 Prescaler
- •The Special Function IO Register – SFIOR
- •The 8-bit Timer/Counter0
- •The Timer/Counter0 Control Register – TCCR0
- •The Timer Counter 0 – TCNT0
- •The 8-bit Timer/Counter1
- •The Timer/Counter1 Control Register – TCCR1
- •The Timer/Counter1 – TCNT1
- •Timer/Counter1 Output Compare RegisterA – OCR1A
- •Timer/Counter1 in PWM Mode
- •Timer/Counter1 Output Compare RegisterB – OCR1B
- •The Watchdog Timer
- •The Watchdog Timer Control Register – WDTCR
- •EEPROM Read/Write Access
- •The EEPROM Address Register – EEAR
- •The EEPROM Data Register – EEDR
- •The EEPROM Control Register – EECR
- •Preventing EEPROM Corruption
- •The Analog Comparator
- •The Analog Comparator Control and Status Register – ACSR
- •The Analog-to-digital Converter, Analog Multiplexer and Gain Stages
- •Feature List:
- •Operation
- •Prescaling and Conversion Timing
- •ADC Noise Canceler Function
- •The ADC Multiplexer Selection Register – ADMUX
- •The ADC Control and Status Register – ADCSR
- •The ADC Data Register – ADCL and ADCH
- •ADLAR = 0:
- •Scanning Multiple Channels
- •ADC Noise-canceling Techniques
- •ADC Characteristics
- •I/O Port B
- •Alternative Functions of Port B
- •The Port B Data Register – PORTB
- •The Port B Data Direction Register – DDRB
- •The Port B Input Pins Address – PINB
- •PORT B as General Digital I/O
- •Alternate Functions of Port B
- •Memory Programming
- •Program and Data Memory Lock Bits
- •Fuse Bits
- •Signature Bytes
- •Calibration Byte
- •Programming the Flash
- •High-voltage Serial Programming
- •High-voltage Serial Programming Algorithm
- •High-voltage Serial Programming Characteristics
- •Low-voltage Serial Downloading
- •Low-voltage Serial Programming Algorithm
- •Data Polling
- •Low-voltage Serial Programming Characteristics
- •Electrical Characteristics
- •Absolute Maximum Ratings
- •DC Characteristics – Preliminary Data
- •Typical Characteristics – PRELIMINARY DATA
- •ATtiny15L Register Summary
- •Ordering Information
ATtiny15L
Tunable Internal RC Oscillator
The internal RC oscillator provides a fixed 1.6 MHz clock (nominal at 5V and 25°C). This internal clock is always the system clock of the ATtiny15L. This oscillator can be calibrated by writing the calibration byte (see page 48) to the OSCCAL register.
The System Clock Oscillator Calibration Register – OSCCAL
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
$31 |
CAL7 |
CAL6 |
CAL5 |
CAL4 |
CAL3 |
CAL2 |
CAL1 |
CAL0 |
OSCCAL |
|
|
|
|
|
|
|
|
|
|
Read/Write |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
|
Initial value |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
Writing the calibration byte to this address will trim the internal oscillator frequency in order to remove process variations. When OSCCAL is zero (initial value), the lowest available frequency is chosen. Writing non-zero values to this register will increase the frequency of the internal oscillator. Writing $FF to the register selects the highest available frequency.
Internal PLL for Fast Peripheral Clock Generation
The internal PLL in ATtiny15L generates a clock frequency that is 16x multiplied from the RC oscillator system clock. If the RC oscillator frequency is the nominal 1.6 MHz, the fast peripheral clock is 25.6 MHz. The fast peripheral clock, or a clock prescaled from that, can be selected as the clock source for Timer/Counter1.
The PLL is locked on the tunable internal RC oscillator and adjusting the tunable internal RC oscillator via the OSCCAL register will adjust the fast peripheral clock at the same time. Timer1 may malfunction if the internal RC oscillator is adjusted beyond 1.75 MHz.
It is recommended not to take the OSCCAL adjustments to a higher frequency than 1.75 MHz in order to keep proper operation of all chip functions.
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