- •Features
- •Disclaimer
- •Overview
- •Block Diagram
- •Pin Descriptions
- •Port B (PB7..PB0)
- •Port C (PC7..PC0)
- •Port D (PD7..PD0)
- •D-/SDATA
- •UGND
- •UVCC
- •UCAP
- •RESET/PC1/dW
- •XTAL1
- •XTAL2/PC0
- •AVR CPU Core
- •Introduction
- •Status Register
- •Stack Pointer
- •TABLE 1.
- •TABLE 2.
- •AVR AT90USB82/162 Memories
- •I/O Memory
- •Clock Systems and their Distribution
- •Clock Switch
- •Exemple of use
- •Swith from external clock to RC clock
- •Switch from RC clock to external clock
- •Clock Sources
- •Default Clock Source
- •External Clock
- •Internal PLL for USB interface
- •Idle Mode
- •Power-down Mode
- •Power-save Mode
- •Standby Mode
- •Analog Comparator
- •Brown-out Detector
- •Watchdog Timer
- •Port Pins
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Watchdog Reset
- •USB Reset
- •Watchdog Timer
- •TABLE 2.
- •TABLE 2.
- •Interrupts
- •TABLE 2.
- •Introduction
- •Configuring the Pin
- •Toggling the Pin
- •Reading the Pin Value
- •TABLE 3.
- •Unconnected Pins
- •Alternate Port Functions
- •Register Description for I/O-Ports
- •Timer/Counter0 and Timer/Counter1 Prescalers
- •Internal Clock Source
- •Prescaler Reset
- •External Clock Source
- •8-bit Timer/Counter0 with PWM
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Normal Mode
- •Fast PWM Mode
- •8-bit Timer/Counter Register Description
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Input Capture Unit
- •Noise Canceler
- •Force Output Compare
- •Normal Mode
- •Fast PWM Mode
- •16-bit Timer/Counter Register Description
- •TABLE 2.
- •TABLE 2.
- •Slave Mode
- •Master Mode
- •Data Modes
- •USART
- •Overview
- •Clock Generation
- •External Clock
- •Frame Formats
- •Parity Bit Calculation
- •TABLE 2.
- •TABLE 3.
- •TABLE 4.
- •Parity Generator
- •TABLE 3.
- •TABLE 2.
- •Receiver Error Flags
- •Parity Checker
- •Disabling the Receiver
- •TABLE 2.
- •Using MPCMn
- •Receiver Flow Control
- •Overview
- •Clock Generation
- •Frame Formats
- •TABLE 2.
- •Data Transfer
- •TABLE 3.
- •USB controller
- •Features
- •Block Diagram
- •Typical Application Implementation
- •Device mode
- •Bus Powered device
- •Introduction
- •Interrupts
- •Power modes
- •Idle mode
- •Power down
- •Freeze clock
- •Memory access capability
- •Memory management
- •PAD suspend
- •D+/D- Read/write
- •Registers description
- •USB general registers
- •USB Software Operating modes
- •USB Device Operating modes
- •Introduction
- •Power-on and reset
- •Endpoint reset
- •USB reset
- •Endpoint selection
- •Endpoint activation
- •Address Setup
- •Detach
- •Remote Wake-up
- •STALL request
- •Special consideration for Control Endpoints
- •STALL handshake and Retry mechanism
- •CONTROL endpoint management
- •Control Write
- •Control Read
- •Overview
- •“Manual” mode
- •Detailed description
- •IN endpoint management
- •“Manual” mode
- •Detailed description
- •Abort
- •Isochronous mode
- •Underflow
- •CRC Error
- •Overflow
- •Interrupts
- •Registers
- •USB device general registers
- •USB device endpoint registers
- •Characteristics
- •Analog Comparator
- •Application Section
- •Boot Reset Fuse
- •Simple Assembly Code Example for a Boot Loader
- •debugWIRE On-chip Debug System
- •Features
- •Overview
- •Physical Interface
- •Software Break Points
- •Limitations of debugWIRE
- •debugWIRE Related Register in I/O Memory
- •Fuse Bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Signal Names
- •Chip Erase
- •Reading the Flash
- •Reading the EEPROM
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •DC Characteristics
- •External Clock Drive Waveforms
- •External Clock Drive
- •Maximum speed vs. VCC
- •Supply Current of IO modules
- •Example 1
- •Example 2
- •Example 3
- •Instruction Set Summary
- •Packaging Information
- •TQFP32
Clock Switch |
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In the AT90USB82/162 product, the Clock Multiplexer and the System Clock Prescaler can be |
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modified by software. |
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Exemple of use |
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The modification can occur when the device enters in USB Suspend mode. It then switches from |
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External Clock to Calibrated RC Oscillator in order to reduce consumption. In such a configura- |
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tion, the External Clock is disabled. |
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The firmware can use the watchdog timer to be woken-up from power-down in order to check if |
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there is an event on the application. |
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If an event occurs on the application or if the USB controller signals a non-idle state on the USB |
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line (Resume for example), the firmware switches the Clock Multiplexer from the Calibrated RC |
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Oscillator to the External Clock. |
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resume |
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1 Resume from Host |
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USB |
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non-Idle |
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Idle |
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(Suspend) |
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non-Idle |
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CPU Clock |
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1 |
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Ext |
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RC |
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Ext |
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External |
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Oscillator |
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RC oscillator |
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3ms |
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watchdog wake-up |
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from power-down |
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Figure 12. Example of clock switching with wake-up from USB Host |
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upstream-resume |
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2 Upstream Resume from device |
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USB |
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non-Idle |
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Idle |
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(Suspend) |
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non-Idle |
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CPU Clock |
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2 |
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Ext |
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RC |
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Ext |
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External |
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Oscillator |
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RC oscillator |
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3ms |
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watchdog wake-up |
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from power-down |
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Figure 13. Example of clock switching with wake-up from Device
26
7707A–AVR–01/07
Clock switch
Algorythm
Swith from external clock to RC clock
Switch from RC clock to external clock
Clock Selection
Register 0 – CLKSEL0
if (Usb_suspend_detected()) |
// if (UDINT.SUSPI == 1) |
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{ |
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Usb_ack_suspend(); |
// UDINT.SUSPI = |
0; |
Usb_freeze_clock(); |
// USBCON.FRZCLK |
= 1; |
Disable_pll(); |
// PLLCSR.PLLE = |
0; |
Enable_RC_clock(); |
// CLKSEL0.RCE = |
1; |
while (!RC_clock_ready()); |
// while (CLKSTA.RCON != 1); |
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Select_RC_clock(); |
// CLKSEL0.CLKS = 0; |
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Disable_external_clock(); |
// CLKSEL0.EXTE = 0; |
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} |
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if (Usb_wake_up_detected()) |
// if (UDINT.WAKEUPI == 1) |
|
{ |
|
|
Usb_ack_wake_up(); |
// UDINT.WAKEUPI |
= 0; |
Enable_external_clock(); |
// CKSEL0.EXTE = |
1; |
while (!External_clock_ready()); |
// while (CLKSTA.EXTON != 1); |
|
Select_external_clock(); |
// CLKSEL0.CLKS = 1; |
|
Enable_pll(); |
// PLLCSR.PLLE = |
1; |
Disable_RC_clock(); |
// CLKSEL0.RCE = |
0; |
while (!Pll_ready()); |
// while (PLLCSR.PLOCK != 1); |
|
Usb_unfreeze_clock(); |
// USBCON.FRZCLK |
= 0; |
} |
|
|
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
RCSUT |
RCSUT |
EXSUT |
EXSUT |
RCE |
EXTE |
- |
CLKS |
CLKSEL |
|
1 |
0 |
1 |
0 |
|
|
|
|
0 |
|
|
|
|
|
|
|
|
|
|
Read/Write |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R |
R/W |
|
Initial Value |
0 |
0 |
0 |
0 |
See Bit Description |
|
|
|
|
• Bit 7-6 – RCSUT[1:0]: SUT for RC oscillator
These 2 bits are the SUT value for the RC Oscillator. If the RC oscillator is selected by fuse bits, the SUT fuse are copied into these bits. A firmware change will not have any effect because this additionnal start-up time is only used after a reset and not after a clock switch.
• Bit 5-4 – EXSUT[1:0]: SUT for External Oscillator / Low Power Oscillator
These 2 bits are the SUT value for the External Oscillator / Low Power Oscillator. If the External oscillator / Low Power Oscillator is selected by fuse bits, the SUT fuse are copyed into these bits. The firmware can modify these bits by writing a new value. This value will be used at the next start of the External Oscillator / Low Power Oscillator.
• Bit 3 – RCE: Enable RC Oscillator
The RCE bit must be written to logic one to enable the RC Oscillator. The RCE bit must be written to logic zero to disable the RC Oscillator.
• Bit 2 – EXTE: Enable External Oscillator / Low Power Oscillator
27
7707A–AVR–01/07
Clock Selection
Register 1 – CLKSEL1
The OSCE bit must be written to logic one to enable External Oscillator / Low Power Oscillator. The OSCE bit must be written to logic zero to disable the External Oscillator / Low Power Oscillator.
• Bit 0 – CLKS: Clock Selector
The CLKS bit must be written to logic one to select the External Oscillator / Low Power Oscillator as CPU clock. The CLKS bit must be written to logic zero to select the RC Oscillator as CPU clock. After a reset, the CLKS bit is set by hardware if the External Oscillator / Low Power Oscillator is selected by the fuse bits configuration.
The firmware has to check if the clock is correctly started before selected it.
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
RCCKS |
RCCKS |
RCCKS |
RCCKS |
EXCKS |
EXCKS |
EXCKS |
EXCKS |
CLKSEL |
|
EL3 |
EL2 |
EL1 |
EL0 |
EL3 |
EL2 |
EL1 |
EL0 |
1 |
|
|
|
|
|
|
|
|
|
|
Read/Write |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
|
Initial Value |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
|
• Bit 7-4 – RCCKSEL[3:0]: CKSEL for RC oscillator
Clock configuration for the RC Oscillator. After a reset, this part of the register is loaded with the 0010b value that corresponds to the RC oscillator. Modifying this value by firmware before switching to RC oscillator is prohibited because the RC clock will not start.
• Bit 3-0 – EXCKSEL[3:0]: CKSEL for External oscillator / Low Power Oscillator
Clock configuration for the External Oscillator / Low Power Oscillator. After a reset, if the External oscillator / Low Power Oscillator is selected by fuse bits, this part of the register is loaded with the fuse configuration. Firmware can modify it to change the start-up time after the clock switch.
Clock Status Register
– CLKSTA
28
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
- |
- |
- |
- |
- |
- |
RCON |
EXTON |
CLKSTA |
|
|
|
|
|
|
|
|
|
|
Read/Write |
R |
R |
R |
R |
R |
R |
R |
R |
|
Initial Value |
0 |
0 |
0 |
0 |
See Bit Description |
|
|
|
|
• Bit 7-2 - Reserved bits
These bits are reserved and will always read as zero.
• Bit 1 – RCON: RC Oscillator On
This bit is set by hardware to one if the RC Oscillator is running.
This bit is set by hardware to zero if the RC Oscillator is stoped.
• Bit 0 – EXTON: External Oscillator / Low Power Oscillator On
This bit is set by hardware to one if the External Oscillator / Low Power Oscillator is running. This bit is set by hardware to zero if the External Oscillator / Low Power Oscillator is stoped.
7707A–AVR–01/07
