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Рыбницкий Филиал Приднестровского Государственного Университета им.Т.Г.Шевченко

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AVR / datasheets / AT90USB82_162.pdf

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Electrical Characteristics

Absolute Maximum Ratings*

Operating Temperature.................................. -55°C to +125°C				*NOTICE: Stresses beyond those listed under “Absolute
				Maximum Ratings” may cause permanent dam-
Storage Temperature ..................................... -65°C to +150°C				age to the device. This is a stress rating only and
				functional operation of the device at these or
Voltage on any Pin except			RESET	other conditions beyond those indicated in the
with respect to Ground(7) .............................-0.5V to VCC+0.5V				operational sections of this specification is not
				implied. Exposure to absolute maximum rating
Voltage on	RESET	with respect to Ground......-0.5V to +13.0V		conditions for extended periods may affect
Maximum Operating Voltage ............................................ 6.0V				device reliability.

DC Current per I/O Pin ............................................... 40.0 mA
DC Current VCC and GND Pins................................ 200.0 mA

DC Characteristics

TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted)

Symbol

Parameter

Condition

Min.(5)

Typ.

Max.(5)

Units

VIL

Input Low Voltage,Except

VCC = 1.8V - 2.4V

-0.5

0.2VCC(1)

XTAL1 and Reset pin

VCC = 2.4V - 5.5V

-0.5

0.3VCC(1)

IL1

Input Low Voltage,

= 1.8V - 5.5V

-0.5

0.1V

(1)

XTAL1 pin

IL2

Input Low Voltage,

= 1.8V - 5.5V

-0.5

0.1V

(1)

RESET pin

Input High Voltage,

VCC = 1.8V - 2.4V

0.7VCC(2)

VCC + 0.5

VIH

Except XTAL1 and

VCC = 2.4V - 5.5V

0.6VCC(2)

VCC + 0.5

RESET pins

VIH1

Input High Voltage,

VCC = 1.8V - 2.4V

0.8VCC(2)

VCC + 0.5

XTAL1 pin

VCC = 2.4V - 5.5V

0.7VCC(2)

VCC + 0.5

IH2

Input High Voltage,

= 1.8V - 5.5V

0.9V

(2)

+ 0.5

RESET pin

VOL

(3)

IOL = 10mA, VCC = 5V

0.7

Output Low Voltage ,

IOL = 5mA, VCC = 3V

0.5

Output High Voltage(4),

IOH = -20mA, VCC = 5V

4.2

IOH = -10mA, VCC = 3V

2.3

IIL

Input Leakage

VCC = 5.5V, pin low

µA

Current I/O Pin

(absolute value)

IIH

Input Leakage

VCC = 5.5V, pin high

µA

Current I/O Pin

(absolute value)

RRST

Reset Pull-up Resistor

kΩ

RPU

I/O Pin Pull-up Resistor

kΩ

253

7707A–AVR–01/07

TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted)

				(Continued)
Symbol	Parameter	Condition			Min.(5)	Typ.	Max.(5)	Units
		Active 1MHz, VCC = 2V					0.8	mA
		(AT90USB82/162V)					0.8	mA
		(AT90USB82/162V)

		Active 4MHz, VCC = 3V					5	mA
		(AT90USB82/162L)					5	mA
		(AT90USB82/162L)

		Active 8MHz, VCC = 5V					18	mA
		(AT90USB82/162)					18	mA
	Power Supply Current(6)	(AT90USB82/162)

ICC		Idle 1MHz, VCC = 2V				0.4	0.75	mA
		Idle 1MHz, VCC = 2V
		(AT90USB82/162V)
		(AT90USB82/162V)
		Idle 4MHz, VCC = 3V					2.2	mA
		(AT90USB82/162L)					2.2	mA
		(AT90USB82/162L)

		Idle 8MHz, VCC = 5V					8	mA
		(AT90USB82/162)					8	mA
		(AT90USB82/162)

	Power-down mode	WDT enabled, VCC = 3V				<10	20	µA
	Power-down mode	WDT disabled, VCC = 3V				<1	3	µA
		WDT disabled, VCC = 3V				<1	3	µA
AVCC	Analog Supply Voltage			VCC - 0.3			VCC + 0.3	V

VACIO	Analog Comparator	VCC = 5V				<10	40	mV
VACIO	Input Offset Voltage	Vin = VCC/2				<10	40	mV
	Input Offset Voltage	Vin = VCC/2
IACLK	Analog Comparator	VCC = 5V	-50				50	nA
IACLK	Input Leakage Current	Vin = VCC/2	-50				50	nA
	Input Leakage Current	Vin = VCC/2
tACID	Analog Comparator	VCC = 2.7V				750		ns
tACID	Propagation Delay	VCC = 4.0V				500		ns
	Propagation Delay	VCC = 4.0V				500
Rusb	USB Serial resistor					22		Ω

Cusb	Ucap capacitor					1		µF

Note: 1.	"Max" means the highest value where the pin is guaranteed to be read as low

2."Min" means the lowest value where the pin is guaranteed to be read as high

3.Although each I/O port can sink more than the test conditions (20mA at VCC = 5V, 10mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed:

AT90USB82/162:

1.)The sum of all IOL, for ports A0-A7, G2, C4-C7 should not exceed 100 mA. 2.)The sum of all IOL, for ports C0-C3, G0-G1, D0-D7 should not exceed 100 mA. 3.)The sum of all IOL, for ports G3-G5, B0-B7, E0-E7 should not exceed 100 mA. 4.)The sum of all IOL, for ports F0-F7 should not exceed 100 mA.

ATmega2560:

1.)The sum of all IOL, for ports J0-J7, A0-A7, G2 should not exceed 200 mA.

2.)The sum of all IOL, for ports C0-C7, G0-G1, D0-D7, L0-L7 should not exceed 200 mA. 3.)The sum of all IOL, for ports G3-G4, B0-B7, H0-B7 should not exceed 200 mA. 4.)The sum of all IOL, for ports E0-E7, G5 should not exceed 100 mA.

5.)The sum of all IOL, for ports F0-F7, K0-K7 should not exceed 100 mA.

If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition.

4.Although each I/O port can source more than the test conditions (20mA at VCC = 5V, 10mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed:

AT90USB82/162:

1)The sum of all IOH, for ports A0-A7, G2, C4-C7 should not exceed 100 mA. 2)The sum of all IOH, for ports C0-C3, G0-G1, D0-D7 should not exceed 100 mA. 3)The sum of all IOH, for ports G3-G5, B0-B7, E0-E7 should not exceed 100 mA.

254

7707A–AVR–01/07

4)The sum of all IOH, for ports F0-F7 should not exceed 100 mA. ATmega2560:

1)The sum of all IOH, for ports J0-J7, G2, A0-A7 should not exceed 200 mA.

2)The sum of all IOH, for ports C0-C7, G0-G1, D0-D7, L0-L7 should not exceed 200 mA. 3)The sum of all IOH, for ports G3-G4, B0-B7, H0-H7 should not exceed 200 mA.

4)The sum of all IOH, for ports E0-E7, G5 should not exceed 100 mA. 5)The sum of all IOH, for ports F0-F7, K0-K7 should not exceed 100 mA.

If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition.

5.All DC Characteristics contained in this datasheet are based on simulation and characterization of other AVR microcontrollers manufactured in the same process technology. These values are preliminary values representing design targets, and will be updated after characterization of actual silicon

6.Values with “Power Reduction Register 1 - PRR1” disabled (0x00).

7.As specified on the USB Electrical chapter, the D+/D- pads can withstand voltages down to -1V applied through a 39 Ohms resistor in series with a 2Ω resistor.

External Clock

Drive Waveforms

Figure 106. External Clock Drive Waveforms

VIH1

VIL1

External Clock Drive

Table 48. External Clock Drive

		VCC=1.8-5.5V		VCC=2.7-5.5V		VCC=4.5-5.5V
Symbol	Parameter	Min.	Max.	Min.	Max.	Min.	Max.	Units

1/tCLCL	Oscillator	0	2	0	8	0	16	MHz
1/tCLCL	Frequency	0	2	0	8	0	16	MHz
tCLCL	Clock Period	500		125		62.5		ns
tCHCX	High Time	200		50		25		ns
tCLCX	Low Time	200		50		25		ns
tCLCH	Rise Time		2.0		1.6		0.5	μs
tCHCL	Fall Time		2.0		1.6		0.5	μs
	Change in period
tCLCL	from one clock		2		2		2	%
	cycle to the next

Note: All DC Characteristics contained in this datasheet are based on simulation and characterization of other AVR microcontrollers manufactured in the same process technology. These values are preliminary values representing design targets, and will be updated after characterization of actual silicon.

255

7707A–AVR–01/07

Maximum speed vs. VCC

Maximum frequency is depending on VCC. As shown in Figure 107 and Figure 108, the Maximum Frequency vs. VCC curve is linear between 1.8V < VCC < 2.7V and between 2.7V < VCC < 4.5V.

Figure 107. Maximum Frequency vs. VCC, AT90USB82/162

8 MHz
4 MHz	Safe Operating Area
1.8V	2.7V	5.5V

Figure 108. Maximum Frequency vs. VCC, AT90USB82/162

16 MHz

8 MHz

Safe Operating Area

2.7V

4.5V

5.5V

256

7707A–AVR–01/07

SPI Timing

Characteristics

See Figure 109 and Figure 110 for details.

Table 49. SPI Timing Parameters

Description

Mode

Min

Typ

Max

SCK period

Master

See Table 58

SCK high/low

Master

50% duty cycle

Rise/Fall time

Master

TBD

Setup

Master

Hold

Master

Out to SCK

Master

0.5 • tsck

SCK to out

Master

SCK to out high

Master

low to out

Slave

SCK period

Slave

4 • tck

SCK high/low(1)

Slave

2 • t

Rise/Fall time

Slave

TBD

Setup

Slave

Hold

Slave

tck

SCK to out

Slave

SCK to

high

Slave

high to tri-state

Slave

low to SCK

Slave

Note:

1. In SPI Programming mode the minimum SCK high/low period is:

-2 tCLCL for fCK < 12 MHz

-3 tCLCL for fCK > 12 MHz

Figure 109. SPI Interface Timing Requirements (Master Mode)

SCK
(CPOL = 0)
		2	2
SCK
(CPOL = 1)
4	5		3
MISO	MSB	...	LSB
(Data Input)	MSB	...	LSB
(Data Input)
		7	8
MOSI	MSB	...	LSB
(Data Output)	MSB	...	LSB
(Data Output)

257

7707A–AVR–01/07

Figure 110. SPI Interface Timing Requirements (Slave Mode)

SCK (CPOL = 0)

SCK (CPOL = 1)

MOSI

(Data Input)

MISO

(Data Output)

10	16

11 11

14			12
MSB	...	LSB
	15		17
MSB	...	LSB	X

Hardware Boot

Figure 111. Hardware Boot Timing Requirements

EntranceTiming

RESET

Characteristics

tSHRH

tHHRH

ALE/HWB

Table 50. Hardware Boot Timings

Symbol	Parameter	Min	Max

tSHRH	HWB low Setup before Reset High	0

	HWB low Hold after Reset High	StartUpTime(SUT) +
tHHRH	HWB low Hold after Reset High	Time Out
		Delay(TOUT)

258

7707A–AVR–01/07

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